From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 7 Sep 2019 05:48:23 +0000 (-0700)
Subject: Make one check $shift(x)? only; change testcase to be 8b
X-Git-Tag: working-ls180~1058^2~13
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e2c2d784c8217e4bcf29fb6b156b6a8285036b80;p=yosys.git

Make one check $shift(x)? only; change testcase to be 8b
---

diff --git a/passes/pmgen/peepopt_shiftmul.pmg b/passes/pmgen/peepopt_shiftmul.pmg
index d4748ae19..e1da52182 100644
--- a/passes/pmgen/peepopt_shiftmul.pmg
+++ b/passes/pmgen/peepopt_shiftmul.pmg
@@ -50,8 +50,9 @@ code
 	if (GetSize(const_factor_cnst) > 20)
 		reject;
 
-	if (GetSize(port(shift, \Y)) > const_factor)
-		reject;
+	if (shift->type.in($shift, $shiftx))
+		if (GetSize(port(shift, \Y)) > const_factor)
+			reject;
 
 	int factor_bits = ceil_log2(const_factor);
 	SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A);
diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index a476133a2..dcf3cacbd 100644
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -16,7 +16,7 @@ select -assert-count 0 t:$shiftx t:* %D
 design -reset
 read_verilog <<EOT
 module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w);
-assign y = 1'b1 >> (w * (3'b110));
+assign y = 1'b1 >> (w * (8'b110));
 endmodule
 EOT
 
@@ -25,7 +25,7 @@ equiv_opt -assert peepopt
 design -load postopt
 clean
 select -assert-count 1 t:$shr
-select -assert-count 1 t:$mul
+select -assert-count 0 t:$mul
 select -assert-count 0 t:$shr t:$mul %% t:* %D
 
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