From: Sean Cross Date: Fri, 19 Apr 2019 05:04:57 +0000 (+0800) Subject: cpu: vexriscv: allow cpu_reset_address to be overridden X-Git-Tag: 24jan2021_ls180~1319^2~1 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e2cf45b8a9ec58abe8a2ad0ab16ab73de45dbffb;p=litex.git cpu: vexriscv: allow cpu_reset_address to be overridden Allow the cpu_reset_address value to be overridden, for example allowing it to be a signal. That way the reset address can be modified after synthesis, in dual-core or debug situations. Signed-off-by: Sean Cross --- diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 1edcc3f7..db05e1fd 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -21,6 +21,7 @@ class VexRiscv(Module, AutoCSR): self.reset = Signal() self.ibus = ibus = wishbone.Interface() self.dbus = dbus = wishbone.Interface() + self.cpu_reset_address = cpu_reset_address self.interrupt = Signal(32) @@ -28,7 +29,7 @@ class VexRiscv(Module, AutoCSR): i_clk=ClockSignal(), i_reset=ResetSignal() | self.reset, - i_externalResetVector=cpu_reset_address, + i_externalResetVector=self.cpu_reset_address, i_externalInterruptArray=self.interrupt, i_timerInterrupt=0,