From: Luke Kenneth Casson Leighton Date: Mon, 2 Jul 2018 04:53:41 +0000 (+0100) Subject: add cocotb test X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e2f789a9ee9b6e43008b3974cbf16d9c662e9f9f;p=pinmux.git add cocotb test --- diff --git a/src/test_bsv/Makefile b/src/test_bsv/Makefile new file mode 100644 index 0000000..3d11e21 --- /dev/null +++ b/src/test_bsv/Makefile @@ -0,0 +1,41 @@ +### Makefile for the cclass project + +TOP_MODULE:=mkpinmux +TOP_FILE:=pinmux.bsv +TOP_DIR:=./ +WORKING_DIR := $(shell pwd) + +BSVINCDIR:= .:%/Prelude:%/Libraries:%/Libraries/BlueNoC +default: gen_verilog + +check-blue: + @if test -z "$$BLUESPECDIR"; then echo "BLUESPECDIR variable not set"; exit 1; fi; + +###### Setting the variables for bluespec compile #$############################ +BSVCOMPILEOPTS:= -check-assert -suppress-warnings G0020 -keep-fires -opt-undetermined-vals -remove-false-rules -remove-empty-rules -remove-starved-rules +BSVLINKOPTS:=-parallel-sim-link 8 -keep-fires +VERILOGDIR:=./verilog/ +BSVBUILDDIR:=./bsv_build/ +BSVOUTDIR:=./bin +################################################################################ + +########## BSIM COMPILE, LINK AND SIMULATE TARGETS ########################## +.PHONY: check-restore +check-restore: + @if [ "$(define_macros)" != "$(old_define_macros)" ]; then make clean ; fi; + +.PHONY: gen_verilog +gen_verilog: check-restore check-blue + @echo Compiling mkTbSoc in Verilog for simulations ... + @mkdir -p $(BSVBUILDDIR); + @mkdir -p $(VERILOGDIR); + bsc -u -verilog -elab -vdir $(VERILOGDIR) -bdir $(BSVBUILDDIR) -info-dir $(BSVBUILDDIR) $(define_macros) -D verilog=True $(BSVCOMPILEOPTS) -verilog-filter ${BLUESPECDIR}/bin/basicinout -p $(BSVINCDIR) -g $(TOP_MODULE) $(TOP_DIR)/$(TOP_FILE) 2>&1 | tee bsv_compile.log + @echo Compilation finished + +############################################################################# + +.PHONY: clean +clean: + rm -rf $(BSVBUILDDIR) *.log $(BSVOUTDIR) ./bbl* + rm -rf verilog obj_dir bsv_src + diff --git a/src/test_bsv/pinmux.bsv b/src/test_bsv/pinmux.bsv index d22c5ea..6abb241 100644 --- a/src/test_bsv/pinmux.bsv +++ b/src/test_bsv/pinmux.bsv @@ -4,7 +4,7 @@ https://bitbucket.org/casl/pinmux. Authors: Neel Gala, Luke - Date of generation: Fri Jun 29 08:13:35 2018 + Date of generation: Mon Jul 2 00:31:10 2018 */ package pinmux; @@ -151,19 +151,20 @@ package pinmux; /*====== This where the muxing starts for each io-cell======*/ + Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero // output muxer for cell idx 0 cell0_mux_out= wrcell0_mux==0?wrgpioa_a0_out: - wrcell0_mux==1?wruart_tx_out: - wrcell0_mux==2?0: // unused - 0; // unused + wrcell0_mux==1?wruart_tx: + wrcell0_mux==2?val0: // unused + val0; // unused // outen muxer for cell idx 0 cell0_mux_outen= wrcell0_mux==0?wrgpioa_a0_outen: // bi-directional wrcell0_mux==1?wrgpioa_a0_outen: // uart_tx is an output - wrcell0_mux==2?0: // unused - 0; // unused + wrcell0_mux==2?val0: // unused + val0; // unused // priority-in-muxer for cell idx 0 rule assign_wrgpioa_a0_in_on_cell0(wrcell0_mux==0); @@ -173,16 +174,16 @@ package pinmux; // output muxer for cell idx 1 cell1_mux_out= wrcell1_mux==0?wrgpioa_a1_out: - wrcell1_mux==1?0: // uart_rx is an input + wrcell1_mux==1?val0: // uart_rx is an input wrcell1_mux==2?wrtwi_sda_out: - 0; // unused + val0; // unused // outen muxer for cell idx 1 cell1_mux_outen= wrcell1_mux==0?wrgpioa_a1_outen: // bi-directional - wrcell1_mux==1?0: // uart_rx is an input + wrcell1_mux==1?val0: // uart_rx is an input wrcell1_mux==2?wrtwi_sda_outen: // bi-directional - 0; // unused + val0; // unused // priority-in-muxer for cell idx 1 rule assign_wrgpioa_a1_in_on_cell1(wrcell1_mux==0); @@ -200,16 +201,16 @@ package pinmux; // output muxer for cell idx 2 cell2_mux_out= wrcell2_mux==0?wrgpioa_a2_out: - wrcell2_mux==1?0: // unused + wrcell2_mux==1?val0: // unused wrcell2_mux==2?wrtwi_scl_out: - 0; // unused + val0; // unused // outen muxer for cell idx 2 cell2_mux_outen= wrcell2_mux==0?wrgpioa_a2_outen: // bi-directional - wrcell2_mux==1?0: // unused + wrcell2_mux==1?val0: // unused wrcell2_mux==2?wrtwi_scl_outen: // bi-directional - 0; // unused + val0; // unused // priority-in-muxer for cell idx 2 rule assign_wrgpioa_a2_in_on_cell2(wrcell2_mux==0); diff --git a/src/test_bsv/tests/Makefile b/src/test_bsv/tests/Makefile new file mode 100644 index 0000000..4745c72 --- /dev/null +++ b/src/test_bsv/tests/Makefile @@ -0,0 +1,54 @@ +############################################################################### +# Copyright (c) 2013 Potential Ventures Ltd +# Copyright (c) 2013 SolarFlare Communications Inc +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Potential Ventures Ltd, +# SolarFlare Communications Inc nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL POTENTIAL VENTURES LTD BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +############################################################################### + +TOPLEVEL_LANG ?= verilog + +PWD=$(shell pwd) +#COCOTB=$(PWD)/../../.. +COCOTB=~/src/verilog/cocotb + +ifeq ($(OS),Msys) +WPWD=$(shell sh -c 'pwd -W') +PYTHONPATH := $(WPWD)/../model;$(PYTHONPATH) +else +WPWD=$(shell pwd) +PYTHONPATH := $(WPWD)/../model:$(PYTHONPATH) +endif + +ifeq ($(TOPLEVEL_LANG),verilog) + VERILOG_SOURCES = $(WPWD)/../verilog/mkpinmux.v +else + $(error "A valid value (verilog or vhdl) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG)") +endif + +TOPLEVEL := mkpinmux +MODULE := test_pinmux + +include $(COCOTB)/makefiles/Makefile.inc +include $(COCOTB)/makefiles/Makefile.sim diff --git a/src/test_bsv/tests/test_pinmux.py b/src/test_bsv/tests/test_pinmux.py new file mode 100644 index 0000000..e2ad15c --- /dev/null +++ b/src/test_bsv/tests/test_pinmux.py @@ -0,0 +1,50 @@ +# Simple tests for an pinmux module +import cocotb +from cocotb.triggers import Timer +from cocotb.result import TestFailure +#from pinmux_model import pinmux_model +import random + + +@cocotb.test() +def pinmux_basic_test(dut): + """Test for 5 + 10""" + yield Timer(2) + A = 5 + B = 10 + + print dir(dut) + + dut.mux_lines_cell0_mux_in = 1 + dut.mux_lines_cell1_mux_in = 2 + dut.mux_lines_cell2_mux_in = 0 + + yield Timer(2) + + if int(dut.X) != pinmux_model(A, B): + raise TestFailure( + "Adder result is incorrect: %s != 15" % str(dut.X)) + else: # these last two lines are not strictly necessary + dut._log.info("Ok!") + + +@cocotb.test() +def pinmux_randomised_test(dut): + """Test for adding 2 random numbers multiple times""" + yield Timer(2) + + for i in range(10): + A = random.randint(0, 15) + B = random.randint(0, 15) + + dut.A = A + dut.B = B + + yield Timer(2) + + if int(dut.X) != pinmux_model(A, B): + raise TestFailure( + "Randomised test failed with: %s + %s = %s" % + (int(dut.A), int(dut.B), int(dut.X))) + else: # these last two lines are not strictly necessary + dut._log.info("Ok!")