From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 4 May 2019 06:01:39 +0000 (+0200)
Subject: Update README
X-Git-Tag: yosys-0.9~141^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e2fb8ebe86f49523168c413c734ce4690d740351;p=yosys.git

Update README

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/README.md b/README.md
index d21d60c97..195329a37 100644
--- a/README.md
+++ b/README.md
@@ -259,11 +259,7 @@ for them:
 
 - The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types
 
-- The ``config`` keyword and library map files
-
-- The ``disable``, ``primitive`` and ``specify`` statements
-
-- Latched logic (is synthesized as logic with feedback loops)
+- The ``config`` and ``disable`` keywords and library map files
 
 
 Verilog Attributes and non-standard features