From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 22 Apr 2019 17:36:27 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into xc7srl
X-Git-Tag: yosys-0.9~171^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e300b1922c13b939231072e83f0ae5c5ff6a558b;p=yosys.git

Merge remote-tracking branch 'origin/master' into xc7srl
---

e300b1922c13b939231072e83f0ae5c5ff6a558b
diff --cc techlibs/xilinx/synth_xilinx.cc
index e84a6714b,d66722195..1449e792f
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -124,14 -118,13 +124,15 @@@ struct SynthXilinxPass : public Pas
  		log("        clean\n");
  		log("\n");
  		log("    map_luts:\n");
 -		log("        techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n");
 +		log("        opt -full\n");
 +		log("        techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v\n");
  		log("        abc -luts 2:2,3,6:5,10,20 [-dff]\n");
  		log("        clean\n");
 -		log("        techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
 +		log("        shregmap -minlen 3 -init -params -enpol any_or_none (without '-nosrl' only)\n");
 +		log("        techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
  		log("        dffinit -ff FDRE   Q INIT -ff FDCE   Q INIT -ff FDPE   Q INIT -ff FDSE   Q INIT \\\n");
  		log("                -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
+ 		log("        clean\n");
  		log("\n");
  		log("    check:\n");
  		log("        hierarchy -check\n");
@@@ -300,15 -275,13 +301,16 @@@
  
  		if (check_label(active, run_from, run_to, "map_luts"))
  		{
 -			Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?");
 +			Pass::call(design, "opt -full");
 +			Pass::call(design, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v");
  			Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
  			Pass::call(design, "clean");
 -			Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
 +			if (!nosrl)
 +				Pass::call(design, "shregmap -minlen 3 -init -params -enpol any_or_none");
 +			Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
  			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
  					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
+ 			Pass::call(design, "clean");
  		}
  
  		if (check_label(active, run_from, run_to, "check"))