From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 29 Aug 2019 01:44:57 +0000 (-0700)
Subject: Add SB_CARRY to ice40_opt test
X-Git-Tag: working-ls180~1088^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e301a3dadbc81a300443713cf7877ea24cc0b2b2;p=yosys.git

Add SB_CARRY to ice40_opt test
---

diff --git a/tests/ice40/ice40_opt.ys b/tests/ice40/ice40_opt.ys
index 18e0d2b8a..b17c69c91 100644
--- a/tests/ice40/ice40_opt.ys
+++ b/tests/ice40/ice40_opt.ys
@@ -1,5 +1,5 @@
 read_verilog -icells -formal <<EOT
-module top(input CI, I0, output CO, O);
+module top(input CI, I0, output [1:0] CO, output O);
     wire A = 1'b0, B = 1'b0;
 	\$__ICE40_CARRY_WRAPPER #(
 		//    A[0]: 1010 1010 1010 1010
@@ -7,18 +7,20 @@ module top(input CI, I0, output CO, O);
 		//    A[2]: 1111 0000 1111 0000
 		//    A[3]: 1111 1111 0000 0000
 		.LUT(~16'b 0110_1001_1001_0110)
-	) fadd (
+	) u0 (
 		.A(A),
 		.B(B),
 		.CI(CI),
 		.I0(I0),
 		.I3(CI),
-		.CO(CO),
+		.CO(CO[0]),
 		.O(O)
 	);
+    SB_CARRY u1 (.I0(~A), .I1(~B), .CI(CI), .CO(CO[1]));
 endmodule
 EOT
 
 equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
 design -load postopt
+select -assert-count 1 t:*
 select -assert-count 1 t:$lut