From: Kenneth Graunke <kenneth@whitecape.org>
Date: Wed, 3 Jul 2013 20:54:53 +0000 (-0700)
Subject: i965: Move intel_context's driconf flags to brw_context.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e33439045d296a218209721cc69176bfef7c4e70;p=mesa.git

i965: Move intel_context's driconf flags to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
---

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 65c99523700..2da46d67d18 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -206,7 +206,7 @@ brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params)
       break;
    }
 
-   if (unlikely(intel->always_flush_batch))
+   if (unlikely(brw->always_flush_batch))
       intel_batchbuffer_flush(brw);
 
    /* We've smashed all state compared to what the normal 3D pipeline
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 9281da1192c..54ffd000387 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -827,8 +827,18 @@ struct brw_context
     */
    bool is_front_buffer_reading;
 
-   /** drirc option cache */
+   /**
+    * drirc options:
+    * @{
+    */
+   bool no_rast;
+   bool always_flush_batch;
+   bool always_flush_cache;
+   bool disable_throttling;
+   bool precompile;
+
    driOptionCache optionCache;
+   /** @} */
 
    GLuint primitive; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
 
@@ -840,7 +850,6 @@ struct brw_context
    bool has_negative_rhw_bug;
    bool has_aa_line_parameters;
    bool has_pln;
-   bool precompile;
 
    /**
     * Some versions of Gen hardware don't do centroid interpolation correctly
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 5d1a7aea209..01e6b2443a7 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -195,7 +195,7 @@ static void brw_emit_prim(struct brw_context *brw,
     * and missed flushes of the render cache as it heads to other parts of
     * the besides the draw code.
     */
-   if (intel->always_flush_cache) {
+   if (brw->always_flush_cache) {
       intel_batchbuffer_emit_mi_flush(brw);
    }
 
@@ -212,7 +212,7 @@ static void brw_emit_prim(struct brw_context *brw,
 
    intel->batch.need_workaround_flush = true;
 
-   if (intel->always_flush_cache) {
+   if (brw->always_flush_cache) {
       intel_batchbuffer_emit_mi_flush(brw);
    }
 }
@@ -221,7 +221,6 @@ static void gen7_emit_prim(struct brw_context *brw,
 			   const struct _mesa_prim *prim,
 			   uint32_t hw_prim)
 {
-   struct intel_context *intel = &brw->intel;
    int verts_per_instance;
    int vertex_access_type;
    int start_vertex_location;
@@ -252,7 +251,7 @@ static void gen7_emit_prim(struct brw_context *brw,
     * and missed flushes of the render cache as it heads to other parts of
     * the besides the draw code.
     */
-   if (intel->always_flush_cache) {
+   if (brw->always_flush_cache) {
       intel_batchbuffer_emit_mi_flush(brw);
    }
 
@@ -266,7 +265,7 @@ static void gen7_emit_prim(struct brw_context *brw,
    OUT_BATCH(base_vertex_location);
    ADVANCE_BATCH();
 
-   if (intel->always_flush_cache) {
+   if (brw->always_flush_cache) {
       intel_batchbuffer_emit_mi_flush(brw);
    }
 }
@@ -477,7 +476,7 @@ retry:
       }
    }
 
-   if (intel->always_flush_batch)
+   if (brw->always_flush_batch)
       intel_batchbuffer_flush(brw);
 
    brw_state_cache_check_size(brw);
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 8a8d2e2e438..0b9a619b630 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -284,7 +284,7 @@ intel_prepare_render(struct brw_context *brw)
     * so we just us the first batch we emitted after the last swap.
     */
    if (intel->need_throttle && intel->first_post_swapbuffers_batch) {
-      if (!intel->disable_throttling)
+      if (!brw->disable_throttling)
          drm_intel_bo_wait_rendering(intel->first_post_swapbuffers_batch);
       drm_intel_bo_unreference(intel->first_post_swapbuffers_batch);
       intel->first_post_swapbuffers_batch = NULL;
@@ -589,17 +589,17 @@ intelInitContext(struct brw_context *brw,
 
    if (driQueryOptionb(&brw->optionCache, "always_flush_batch")) {
       fprintf(stderr, "flushing batchbuffer before/after each draw call\n");
-      intel->always_flush_batch = 1;
+      brw->always_flush_batch = 1;
    }
 
    if (driQueryOptionb(&brw->optionCache, "always_flush_cache")) {
       fprintf(stderr, "flushing GPU caches before/after each draw call\n");
-      intel->always_flush_cache = 1;
+      brw->always_flush_cache = 1;
    }
 
    if (driQueryOptionb(&brw->optionCache, "disable_throttling")) {
       fprintf(stderr, "disabling flush throttling\n");
-      intel->disable_throttling = 1;
+      brw->disable_throttling = 1;
    }
 
    return true;
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index 46fe7f72881..bcaad310047 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -158,11 +158,6 @@ struct intel_context
 
    GLuint stats_wm;
 
-   bool no_rast;
-   bool always_flush_batch;
-   bool always_flush_cache;
-   bool disable_throttling;
-
    int driFd;
 
    __DRIcontext *driContext;