From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Fri, 8 Mar 2019 10:47:02 +0000 (+0000)
Subject: dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)
X-Git-Tag: v19.0.0.0~1007
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e36839e7780df11065ab0a08abaf3fcf68135aa7;p=gem5.git

dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)

For SGIs and PPIs:
* When ARE is 1 (only value supported in gem5) for the Security state of
an interrupt, the field for that interrupt is RES0 and an implementation
is permitted to make the field RAZ/WI in this case.

Change-Id: I6da2a89b1c848d458f42540e0113e7139b910abb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17630
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---

diff --git a/src/dev/arm/gic_v3_distributor.cc b/src/dev/arm/gic_v3_distributor.cc
index 148de5a19..f261b295b 100644
--- a/src/dev/arm/gic_v3_distributor.cc
+++ b/src/dev/arm/gic_v3_distributor.cc
@@ -578,6 +578,10 @@ Gicv3Distributor::write(Addr addr, uint64_t data, size_t size,
         // Interrupt Clear-Enable Registers
         int first_intid = (addr - GICD_ICENABLER.start()) * 8;
 
+        if (isNotSPI(first_intid)) {
+            return;
+        }
+
         for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines;
              i++, int_id++) {