From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 20 Jun 2022 15:10:59 +0000 (+0100)
Subject: add power_pipeline.jpg to svp64 primer
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e36b59c1e3f13b3732a19b517c999f441c66ad73;p=libreriscv.git

add power_pipeline.jpg to svp64 primer
---

diff --git a/svp64-primer/img/power_pipelines.jpg b/svp64-primer/img/power_pipelines.jpg
new file mode 100644
index 000000000..764711fbd
Binary files /dev/null and b/svp64-primer/img/power_pipelines.jpg differ
diff --git a/svp64-primer/summary.tex b/svp64-primer/summary.tex
index 1e14acf31..e7bfb5d0c 100644
--- a/svp64-primer/summary.tex
+++ b/svp64-primer/summary.tex
@@ -38,6 +38,13 @@ idle for long periods.
 Simple-V has been specifically and carefully crafted to respect
 the Power ISA's Supercomputing pedigree.
 
+\begin{figure}[hb]
+    \centering
+	\includegraphics[width=0.6\linewidth]{power_pipelines}
+	\caption{Showing how SV fits in between Decode and Issue}
+	\label{fig:power_pipelines}
+\end{figure}
+
 \pagebreak
 
 \subsection{What is SIMD?}