From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 6 Nov 2018 16:11:12 +0000 (+0000)
Subject: add debug info on rv_sr
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e36f450e9a8e22c2a876b6d83d0cc3593b370f56;p=riscv-isa-sim.git

add debug info on rv_sr
---

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 6475435..c7872bc 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -551,7 +551,10 @@ sv_reg_t sv_proc_t::rv_sl(sv_reg_t const & lhs, sv_reg_t const & rhs,
     uint64_t vlhs = 0;
     uint64_t vrhs = 0;
     if (rv_int_op_prepare(lhs, rhs, vlhs, vrhs, bitwidth)) {
-        return lhs << rv_and(rhs, sv_reg_t(dflt_bitwidth-1U));
+        sv_reg_t result = lhs << rv_and(rhs, sv_reg_t(dflt_bitwidth-1U));
+        fprintf(stderr, "sl result %lx %lx %lx\n",
+                (uint64_t)lhs, (uint64_t)rhs, (uint64_t)(result));
+        return result;
     }
     uint64_t result = vlhs << (vrhs & (bitwidth-1));
     return rv_int_op_finish(lhs, rhs, result, bitwidth);
@@ -569,10 +572,16 @@ sv_reg_t sv_proc_t::rv_sr(sv_reg_t const & lhs, sv_reg_t const & rhs,
     uint64_t vlhs = 0;
     uint64_t vrhs = 0;
     if (rv_int_op_prepare(lhs, rhs, vlhs, vrhs, bitwidth)) {
-        return lhs >> rv_and(rhs, sv_reg_t(dflt_bitwidth-1U));
+        sv_reg_t result = lhs >> rv_and(rhs, sv_reg_t(dflt_bitwidth-1U));
+        fprintf(stderr, "sr result %lx %lx %lx\n",
+                (uint64_t)lhs, (uint64_t)rhs, (uint64_t)(result));
+        return result;
     }
     uint64_t result = vlhs >> (vrhs & (bitwidth-1));
-    return rv_int_op_finish(lhs, rhs, result, bitwidth);
+    sv_reg_t sresult = rv_int_op_finish(lhs, rhs, result, bitwidth);
+        fprintf(stderr, "sr result %lx %lx %lx bw %d\n",
+                (uint64_t)lhs, (uint64_t)rhs, (uint64_t)(sresult), bitwidth);
+    return sresult;
 }
 
 bool sv_proc_t::rv_lt(sv_reg_t const & lhs, sv_reg_t const & rhs)