From: Eddie Hung Date: Thu, 29 Aug 2019 01:51:14 +0000 (-0700) Subject: LX -> LP X-Git-Tag: working-ls180~1075^2^2~19 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e3709e5ee6b28c1156b4768373e244c32c7c5aba;p=yosys.git LX -> LP --- diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 34134d02a..fe80c998d 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -3,7 +3,7 @@ // `define SB_DFF_REG reg Q `define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif -`define ABC_ARRIVAL_LX(TIME) `ifdef ICE40_LX (* abc_arrival=TIME *) `endif +`define ABC_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc_arrival=TIME *) `endif `define ABC_ARRIVAL_U(TIME) `ifdef ICE40_U (* abc_arrival=TIME *) `endif // SiliconBlue IO Cells