From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 16 Oct 2018 14:53:16 +0000 (+0100)
Subject: add section on different RV standards
X-Git-Tag: convert-csv-opcode-to-binary~4924
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e372c175aaa82dc4936ee70d58ae8f6d80a89d24;p=libreriscv.git

add section on different RV standards
---

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index f038e9903..1522233ac 100644
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -1068,6 +1068,10 @@ CSR Register table is either 4 16-bit entries or (if the U-Mode is
 zero) only 2 16-bit entries (M-Mode CSR table only).  Likewise for
 the Predication CSR tables.
 
+RV32E is the most likely candidate for simply detecting that registers
+are marked as "vectorised", and generating an appropriate exception
+for the VL loop to be implemented in software.
+
 ## RV128
 
 RV128 has not been especially considered, here, however it has some