From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 18 Feb 2022 21:01:51 +0000 (+0000)
Subject: add DRAM class to DDR3Soc
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e376d903fc7bc4d74374e929be17221c2379710b;p=ls2.git

add DRAM class to DDR3Soc
---

diff --git a/src/ls2.py b/src/ls2.py
index 7fe9ca3..1a7974e 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -297,7 +297,7 @@ if __name__ == "__main__":
                                          "odt":4, "ras":4, "cas":4, "we":4})
 
     # set up the SOC
-    soc = DDR3SoC(fpga, dram_cls,
+    soc = DDR3SoC(dram_cls=dram_cls,
                   ddrphy_addr=0xff000000, # DRAM firmware init base
                   dramcore_addr=0x80000000,
                   ddr_addr=0x10000000,