From: Xan <Xan@web>
Date: Wed, 25 Apr 2018 11:41:54 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~5519
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e377793637fe2eefc7f5e6b48a79ff1ed8480caf;p=libreriscv.git

---

diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
index 38026f87e..b76f22a70 100644
--- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
+++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
@@ -27,7 +27,7 @@ Values for mm field (bits 12:13 above):
 * mm = 10 -> use v1 as predicate mask, and use global saturation / rounding settings
 * mm = 11 -> use ~v1 as predicate mask, and use global saturation / rounding settings
 
-## Register file
+## Register file comparison
 
 The default Harmonised RVP GPR register file is divided into a lower bank of Vector[INT8] and an upper bank of Vector[INT16].
 In contrast, the Andes Packed SIMD ISA permits any GPR to be used for either INT8 or INT16 vector operations