From: lkcl Date: Sun, 21 Aug 2022 16:36:52 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~803 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e37cf0c408da0f246873f5a9caba1a58c6101926;p=libreriscv.git --- diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn index 3bfc3e8c1..2e136f8ad 100644 --- a/openpower/sv/normal.mdwn +++ b/openpower/sv/normal.mdwn @@ -36,7 +36,7 @@ is as if the When Rc=1 the CR element however is still stored in the CR regfile, even if the test failed. See appendix for details. * **Pack/Unpack** mode, only available when SUBVL is vec2/3/4, performs basic structure packing on sub-elements. Bits 4-5 (normally elwidth) are -taken up as Pack/Unpack bits. +taken up as Pack/Unpack bits. Saturation may be simultaneously enabled. Note that ffirst and reduce modes are not anticipated to be high-performance in some implementations. ffirst due to interactions with VL, and reduce due to it requiring additional operations to produce a result. normal, saturate and pred-result are however inter-element independent and may easily be parallelised to give high performance, regardless of the value of VL.