From: Eddie Hung Date: Tue, 6 Aug 2019 23:42:25 +0000 (-0700) Subject: Use IdString::begins_with() X-Git-Tag: working-ls180~1151^2~11 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e38f40af5b7cdd5c8b896ffba17069bd65f01f29;p=yosys.git Use IdString::begins_with() --- diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index 4758c6d4d..bb5ea2932 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -297,7 +297,7 @@ struct FirrtlWorker std::string cell_type = fid(cell->type); std::string instanceOf; // If this is a parameterized module, its parent module is encoded in the cell type - if (cell->type.substr(0, 8) == "$paramod") + if (cell->type.begins_with("$paramod")) { std::string::iterator it; for (it = cell_type.begin(); it < cell_type.end(); it++) @@ -776,7 +776,7 @@ struct FirrtlWorker } // This may be a parameterized module - paramod. - if (cell->type.substr(0, 8) == "$paramod") + if (cell->type.begins_with("$paramod")) { process_instance(cell, wire_exprs); continue; diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 42c65143d..e770d4b4b 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -828,8 +828,8 @@ namespace { void check() { - if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || cell->type.substr(0,10) == "$fmcombine" || - cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:") + if (cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") || + cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:")) return; if (cell->type.in("$not", "$pos", "$neg")) { @@ -2553,8 +2553,8 @@ void RTLIL::Cell::check() void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) { - if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || type.substr(0,10) == "$fmcombine" || - type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:") + if (type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") || + type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:")) return; if (type == "$mux" || type == "$pmux") { diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 1cfe71473..d7e036431 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -276,20 +276,24 @@ namespace RTLIL return std::string(c_str() + pos, len); } + int compare(size_t pos, size_t len, const char* s) const { + return strncmp(c_str()+pos, s, len); + } + bool begins_with(const char* prefix) const { size_t len = strlen(prefix); if (size() < len) return false; - return substr(0, len) == prefix; + return compare(0, len, prefix); } bool ends_with(const char* suffix) const { size_t len = strlen(suffix); if (size() < len) return false; - return substr(size()-len) == suffix; + return compare(size()-len, len, suffix); } size_t size() const { - return str().size(); + return strlen(c_str()); } bool empty() const { diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 213437c01..19bf531cf 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -48,7 +48,7 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, RTLIL::Cell *cell = i2.second; if (design->has(cell->type)) continue; - if (cell->type.substr(0, 1) == "$" && cell->type.substr(0, 3) != "$__") + if (cell->type.begins_with("$__")) continue; for (auto &pattern : celltypes) if (patmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str())) @@ -143,7 +143,7 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, // Return the "basic" type for an array item. std::string basic_cell_type(const std::string celltype, int pos[3] = nullptr) { std::string basicType = celltype; - if (celltype.substr(0, 7) == "$array:") { + if (celltype.compare(0, strlen("$array:"), "$array:")) { int pos_idx = celltype.find_first_of(':'); int pos_num = celltype.find_first_of(':', pos_idx + 1); int pos_type = celltype.find_first_of(':', pos_num + 1); @@ -194,14 +194,14 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check std::vector connections_to_add_name; std::vector connections_to_add_signal; - if (cell->type.substr(0, 7) == "$array:") { + if (cell->type.begins_with("$array:")) { int pos[3]; basic_cell_type(cell->type.str(), pos); int pos_idx = pos[0]; int pos_num = pos[1]; int pos_type = pos[2]; - int idx = atoi(cell->type.str().substr(pos_idx + 1, pos_num).c_str()); - int num = atoi(cell->type.str().substr(pos_num + 1, pos_type).c_str()); + int idx = std::stoi(cell->type.str().substr(pos_idx + 1, pos_num)); + int num = std::stoi(cell->type.str().substr(pos_num + 1, pos_type)); array_cells[cell] = std::pair(idx, num); cell->type = cell->type.str().substr(pos_type + 1); } @@ -422,8 +422,8 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check for (auto &conn : cell->connections_) { int conn_size = conn.second.size(); RTLIL::IdString portname = conn.first; - if (portname.substr(0, 1) == "$") { - int port_id = atoi(portname.substr(1).c_str()); + if (portname.begins_with("$")) { + int port_id = std::stoi(portname.substr(1)); for (auto &wire_it : mod->wires_) if (wire_it.second->port_id == port_id) { portname = wire_it.first; @@ -457,9 +457,8 @@ void hierarchy_worker(RTLIL::Design *design, std::setcells()) { std::string celltype = cell->type.str(); - if (celltype.substr(0, 7) == "$array:") { + if (celltype.compare(0, strlen("$array:"), "$array:")) celltype = basic_cell_type(celltype); - } if (design->module(celltype)) hierarchy_worker(design, used, design->module(celltype), indent+4); } @@ -521,9 +520,8 @@ int find_top_mod_score(Design *design, Module *module, dict &db) for (auto cell : module->cells()) { std::string celltype = cell->type.str(); // Is this an array instance - if (celltype.substr(0, 7) == "$array:") { + if (celltype.compare(0, strlen("$array:"), "$array:")) celltype = basic_cell_type(celltype); - } // Is this cell a module instance? auto instModule = design->module(celltype); // If there is no instance for this, issue a warning. diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index d712736c1..450626f4a 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -63,11 +63,11 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) log_assert(GetSize(sig_set) == GetSize(sig_clr)); - if (cell->type.substr(0,8) == "$_DFFSR_") { + if (cell->type.begins_with("$_DFFSR_")) { pol_set = cell->type[9] == 'P' ? State::S1 : State::S0; pol_clr = cell->type[10] == 'P' ? State::S1 : State::S0; } else - if (cell->type.substr(0,11) == "$_DLATCHSR_") { + if (cell->type.begins_with("$_DLATCHSR_")) { pol_set = cell->type[12] == 'P' ? State::S1 : State::S0; pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0; } else @@ -198,9 +198,9 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) { IdString new_type; - if (cell->type.substr(0,8) == "$_DFFSR_") + if (cell->type.begins_with("$_DFFSR_")) new_type = stringf("$_DFF_%c_", cell->type[8]); - else if (cell->type.substr(0,11) == "$_DLATCHSR_") + else if (cell->type.begins_with("$_DLATCHSR_")) new_type = stringf("$_DLATCH_%c_", cell->type[11]); else log_abort(); @@ -278,7 +278,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) sig_c = dff->getPort("\\C"); val_cp = RTLIL::Const(dff->type == "$_DFF_P_", 1); } - else if (dff->type.substr(0,6) == "$_DFF_" && dff->type.substr(9) == "_" && + else if (dff->type.begins_with("$_DFF_") && dff->type.substr(9) == "_" && (dff->type[6] == 'N' || dff->type[6] == 'P') && (dff->type[7] == 'N' || dff->type[7] == 'P') && (dff->type[8] == '0' || dff->type[8] == '1')) { @@ -290,7 +290,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) val_rp = RTLIL::Const(dff->type[7] == 'P', 1); val_rv = RTLIL::Const(dff->type[8] == '1', 1); } - else if (dff->type.substr(0,7) == "$_DFFE_" && dff->type.substr(9) == "_" && + else if (dff->type.begins_with("$_DFFE_") && dff->type.substr(9) == "_" && (dff->type[7] == 'N' || dff->type[7] == 'P') && (dff->type[8] == 'N' || dff->type[8] == 'P')) { sig_d = dff->getPort("\\D"); @@ -428,7 +428,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) return true; } - log_assert(dff->type.substr(0,6) == "$_DFF_"); + log_assert(dff->type.begins_with("$_DFF_")); dff->type = stringf("$_DFF_%c_", + dff->type[6]); dff->unsetPort("\\R"); } @@ -452,7 +452,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff) return true; } - log_assert(dff->type.substr(0,7) == "$_DFFE_"); + log_assert(dff->type.begins_with("$_DFFE_")); dff->type = stringf("$_DFF_%c_", + dff->type[7]); dff->unsetPort("\\E"); }