From: Thomas Watson Date: Tue, 11 May 2021 02:02:29 +0000 (-0500) Subject: tests.hdl.dsl: add tests for mis-nested Switch/Case and FSM/State statements X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e393618b0eca722ce958bc624d522677bbffda7e;p=nmigen.git tests.hdl.dsl: add tests for mis-nested Switch/Case and FSM/State statements --- diff --git a/tests/test_hdl_dsl.py b/tests/test_hdl_dsl.py index a2d0c96..5156eab 100644 --- a/tests/test_hdl_dsl.py +++ b/tests/test_hdl_dsl.py @@ -504,6 +504,15 @@ class DSLTestCase(FHDLTestCase): with m.If(self.s2): pass + def test_Case_wrong_nested(self): + m = Module() + with m.Switch(self.s1): + with m.Case(0): + with self.assertRaisesRegex(SyntaxError, + r"^Case is not permitted outside of Switch$"): + with m.Case(1): + pass + def test_FSM_basic(self): a = Signal() b = Signal() @@ -660,6 +669,23 @@ class DSLTestCase(FHDLTestCase): with m.If(self.s2): pass + def test_State_outside_FSM_wrong(self): + m = Module() + with self.assertRaisesRegex(SyntaxError, + r"^FSM State is not permitted outside of FSM"): + with m.State("FOO"): + pass + + + def test_FSM_State_wrong_nested(self): + m = Module() + with m.FSM(): + with m.State("FOO"): + with self.assertRaisesRegex(SyntaxError, + r"^FSM State is not permitted outside of FSM"): + with m.State("BAR"): + pass + def test_auto_pop_ctrl(self): m = Module() with m.If(self.w1):