From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 28 Sep 2020 13:09:38 +0000 (+0000)
Subject: worked out how to do pad instances in experiment4
X-Git-Tag: partial-core-ls180-gdsii~65
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e393d327ae68a996eeaca12ca6e94914dbdf4186;p=soclayout.git

worked out how to do pad instances in experiment4
---

diff --git a/experiments4/coriolis2/ioring.py b/experiments4/coriolis2/ioring.py
index 2227b20..b362811 100644
--- a/experiments4/coriolis2/ioring.py
+++ b/experiments4/coriolis2/ioring.py
@@ -3,12 +3,36 @@
 from helpers import l, u, n
 
 
-chip = { 'pads.ioPadGauge' : 'pxlib'
-       , 'pads.south'      : [ 'a_1', 'p_vddick_0', 'p_vssick_0' , 'a_0'       ]
-       , 'pads.east'       : [ 'a_2', 'a_3'       , 'b_3'        , 'b_2'       ]
-       , 'pads.north'      : [ 'b_1', 'p_vddeck_0', 'b_0'        , 'p_vsseck_0', 'rst' ]
-       , 'pads.west'       : [ 'f_3', 'f_2'       , 'p_clk_0', 'f_1'       , 'f_0'     ]
-       , 'core.size'       : ( l( 800), l( 800) )
-       , 'chip.size'       : ( l(2000), l(2000) )
-       , 'chip.clockTree'  : True
+chip = { 'pads.ioPadGauge' : 'pxlib',
+
+      #   | Instance  | Pad   | To Core          | From Core     | Enable    |
+       'pads.instances' :[
+        # "a" input.
+        [ 'p_a0'    , 'a(0)', 'a(0)' ],
+        [ 'p_a1'    , 'a(1)', 'a(1)' ],
+        [ 'p_a2'    , 'a(2)', 'a(2)' ],
+        [ 'p_a3'    , 'a(3)', 'a(3)' ],
+        # "b" input.
+        [ 'p_b0'    , 'b(0)', 'b(0)' ],
+        [ 'p_b1'    , 'b(1)', 'b(1)' ],
+        [ 'p_b2'    , 'b(2)', 'b(2)' ],
+        [ 'p_b3'    , 'b(3)', 'b(3)' ],
+        # "f" output.
+        [ 'p_f0'    , 'f(0)',   'f(0)' ], # , 'f_oe' ],
+        [ 'p_f1'    , 'f(1)',   'f(1)' ], # , 'f_oe' ],
+        [ 'p_f2'    , 'f(2)',   'f(2)' ], # , 'f_oe' ],
+        [ 'p_f3'    , 'f(3)',   'f(3)' ], # , 'f_oe' ],
+        ],
+        'pads.south'      :
+            [ 'p_a1', 'p_vddick_0', 'p_vssick_0' , 'p_a0'       ],
+       'pads.east'       :
+            [ 'p_a2', 'p_a3'       , 'p_b3'        , 'p_b2'       ],
+       'pads.north'      :
+            [ 'p_b1', 'p_vddeck_0', 'p_b0'        , 'p_vsseck_0', 'rst' ],
+       'pads.west'       :
+            [ 'p_f3', 'p_f2'       , 'p_clk_0', 'p_f1'       , 'p_f0' ],
+       'core.size'       : ( l( 800), l( 800) ),
+       'chip.size'       : ( l(2000), l(2000) ),
+       'chip.clockTree'  : True,
        }
+