From: lkcl <lkcl@web>
Date: Wed, 25 May 2022 11:47:14 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2097
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e3954be5f426997a9c45fd5e60ed74a30a9708d8;p=libreriscv.git

---

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index 2326f6c59..ab036f173 100644
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -74,6 +74,12 @@ In all existing Power ISA Scalar conversion instructions, all
 operands are FPRs, even if the format of the source or destination
 data is actually a scalar integer.
 
+*(This is based on an assumption
+that VSX will be implemented, and VSX is not part of the SFFS Compliancy
+Level. An earlier version of the Power ISA used to have similar instructions:
+they were deprecated due to this incorrect assumption that VSX would
+always be present).*
+
 Note that source and destination widths can be overridden by SimpleV
 SVP64, and that SVP64 also has Saturation Modes *in addition*
 to those independently described here. SVP64 Overrides and Saturation