From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 26 Jan 2020 13:08:52 +0000 (+0000)
Subject: whoops sort out page hierarchy
X-Git-Tag: convert-csv-opcode-to-binary~3680
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e395c30c40fad375adecb5697a1b7f4076b9aae5;p=libreriscv.git

whoops sort out page hierarchy
---

diff --git a/3d_gpu/architecture.mdwn b/3d_gpu/architecture.mdwn
index 83f9c3f8e..ca20268e1 100644
--- a/3d_gpu/architecture.mdwn
+++ b/3d_gpu/architecture.mdwn
@@ -20,7 +20,7 @@ There are no separate scalar ALUs and separate SIMD ALUs. The ALUs are dynamical
 
 The only reason this design can even remotely be considered is down to the use of standard python Software Engineering Object-Orientated techniques, on top of nmigen, which industry-standard HDLs such as VHDL and Verilog completely lack.
 
-See [[3d_gpu/architecture/dynamic_simd]] for details.
+See [[architecture/dynamic_simd]] for details.
 
 # Dynamic Pipeline length adjustment
 
@@ -34,7 +34,7 @@ The only reason why this ingenious and elegant trick (deployed first by IBM in t
 
 # Memory and Cache arrangement
 
-Section TODO, with own page [[3d_gpu/architecture/memory_and_cache]]  LD/ST accesses are controlled by the 6600-style Dependency Matrices
+Section TODO, with own page [[architecture/memory_and_cache]]  LD/ST accesses are controlled by the 6600-style Dependency Matrices
 
 # Bus arrangement
 
diff --git a/3d_gpu/architecture/3d_gpu/architecture/dynamic_simd/eq.mdwn b/3d_gpu/architecture/3d_gpu/architecture/dynamic_simd/eq.mdwn
deleted file mode 100644
index 974d80885..000000000
--- a/3d_gpu/architecture/3d_gpu/architecture/dynamic_simd/eq.mdwn
+++ /dev/null
@@ -1,14 +0,0 @@
-# Boolean truth table
-
-[[!table  data="""
-p2p1p0 | o0       | o1 | o2 | o3
-++++++ | ++++++++ | ++++++++ | ++++++++ | ++
-0 0 0  | &(eq0-3) | 0 | 0 | 0
-0 0 1  | eq0      | &(eq1-3)  | 0  | 0
-0 1 0  | &(eq0-1) | 0 | &(eq2-3)  | 0
-0 1 1  | eq0      | eq1 | &(eq2-3) | 0
-1 0 0  | &(eq0-2) | 0 | 0 | eq3
-1 0 1  | eq0      | &(eq01-2) | 0 | eq3
-1 1 0  | &(eq0-1) | 0 | eq2 | eq3
-1 1 1  | eq0      | eq1 | eq2 | eq3
-"""]]
diff --git a/3d_gpu/architecture/dynamic_simd.mdwn b/3d_gpu/architecture/dynamic_simd.mdwn
index dd0f36582..b673d6d40 100644
--- a/3d_gpu/architecture/dynamic_simd.mdwn
+++ b/3d_gpu/architecture/dynamic_simd.mdwn
@@ -8,6 +8,6 @@ Basic principle: when all partition gates are open the ALU is subdivided into is
 
 Pages below describe the basic features of each and track the relevant bugreports.
 
-* [[3d_gpu/architecture/dynamic_simd/eq]]
-* [[3d_gpu/architecture/dynamic_simd/add]]
-* [[3d_gpu/architecture/dynamic_simd/mul]]
+* [[dynamic_simd/eq]]
+* [[dynamic_simd/add]]
+* [[dynamic_simd/mul]]
diff --git a/3d_gpu/architecture/dynamic_simd/eq.mdwn b/3d_gpu/architecture/dynamic_simd/eq.mdwn
new file mode 100644
index 000000000..974d80885
--- /dev/null
+++ b/3d_gpu/architecture/dynamic_simd/eq.mdwn
@@ -0,0 +1,14 @@
+# Boolean truth table
+
+[[!table  data="""
+p2p1p0 | o0       | o1 | o2 | o3
+++++++ | ++++++++ | ++++++++ | ++++++++ | ++
+0 0 0  | &(eq0-3) | 0 | 0 | 0
+0 0 1  | eq0      | &(eq1-3)  | 0  | 0
+0 1 0  | &(eq0-1) | 0 | &(eq2-3)  | 0
+0 1 1  | eq0      | eq1 | &(eq2-3) | 0
+1 0 0  | &(eq0-2) | 0 | 0 | eq3
+1 0 1  | eq0      | &(eq01-2) | 0 | eq3
+1 1 0  | &(eq0-1) | 0 | eq2 | eq3
+1 1 1  | eq0      | eq1 | eq2 | eq3
+"""]]