From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 19 Apr 2021 17:38:27 +0000 (+0000)
Subject: code-comments
X-Git-Tag: LS180_RC3~98
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e39c974c71a6bae1ef4d4ebbd0225c7a56e5b051;p=soclayout.git

code-comments
---

diff --git a/experiments10_verilog/add.py b/experiments10_verilog/add.py
index fa7c2f0..3e66b26 100644
--- a/experiments10_verilog/add.py
+++ b/experiments10_verilog/add.py
@@ -21,7 +21,8 @@ class ADD(Elaboratable):
         self.b      = Signal(width)
         self.f      = Signal(width)
 
-        # set up JTAG
+        # set up JTAG - use an irwidth of 4, up to 16 ircodes (1<<4).
+        # change this to add more Wishbone interfaces: see below
         self.jtag = TAP(ir_width=4)
         self.jtag.bus.tck.name = 'jtag_tck'
         self.jtag.bus.tms.name = 'jtag_tms'