From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 1 Jul 2020 16:47:29 +0000 (+0100)
Subject: print out msr for debug
X-Git-Tag: div_pipeline~183
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e3a2ff27bf45a0609a661579e5ef570c35bb161a;p=soc.git

print out msr for debug
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 488df5ce..b79b9099 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -583,6 +583,8 @@ class ISACaller:
                         self.spr[name] = output
                     else:
                         self.namespace[name].eq(output)
+                    if name == 'MSR':
+                        print ('msr written', hex(self.msr.value))
                 else:
                     regnum = yield getattr(self.decoder, name)
                     print('writing reg %d %s' % (regnum, str(output)))