From: Luke Kenneth Casson Leighton Date: Sun, 20 Dec 2020 23:31:40 +0000 (+0000) Subject: table cleanup X-Git-Tag: convert-csv-opcode-to-binary~1114 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e3b1cc75618ac5a6295c24e44622ec1c465b2a1b;p=libreriscv.git table cleanup --- diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index ccef9b21b..7a69cd7a7 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -67,7 +67,7 @@ is defined in the Prefix Fields section. (shows both PowerISA v3.1 instructions as well as new SVP instructions; empty spaces are yet-to-be-allocated Illegal Instructions) | 6:11 | ---000 | ---001 | ---010 | ---011 | ---100 | ---101 | ---110 | ---111 | -| ---- | ------ | ------ | ------ | ------ | ------ | ------ | ------ | ------ | +|------|--------|--------|--------|--------|--------|--------|--------|--------| |000---| 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | 8LS | |001---| | | | | | | | | |010---| 8RR | | | | `SVP64`| `SVP64`| `SVP64`| `SVP64`| @@ -79,13 +79,13 @@ is defined in the Prefix Fields section. ## Prefix Fields -| Prefix Field Name | Field | Value | Description | -|---------------------|---------|-------|--------------------------------------------| -| PO (Primary Opcode) | `0:5` | `1` | Indicates this is Prefixed 64-bit | +| Prefix Field Name | Field | Value | Description | +|---------------------|---------|-------|------------------------------------| +| PO (Primary Opcode) | `0:5` | `1` | Indicates this is Prefixed 64-bit | | `RM[0]` | `6` | | Bit 0 of the Remapped Encoding | -| SVP64_7 | `7` | `1` | Indicates this is SVP64 | -| `RM[1]` | `8` | | Bit 1 of the Remapped Encoding | -| SVP64_9 | `9` | `1` | Indicates this is SVP64 | +| SVP64_7 | `7` | `1` | Indicates this is SVP64 | +| `RM[1]` | `8` | | Bit 1 of the Remapped Encoding | +| SVP64_9 | `9` | `1` | Indicates this is SVP64 | | `RM[2:23]` | `10:31` | | Bits 2-23 of the Remapped Encoding | @@ -105,31 +105,31 @@ is based on whether the number of src operands is 2 or 3. ## RM-1P-3S1D -| Field Name | Field bits | Description | -|------------|------------|------------------------------------------------| -| MASK\_KIND | `0` | Execution Mask Kind | -| MASK | `1:3` | Execution Mask | -| ELWIDTH | `4:5` | Element Width | -| SUBVL | `6:7` | Sub-vector length | -| Rdest\_EXTRA2 | `8:9` | extra bits for Rdest (R\*\_EXTRA2 Encoding) | -| Rsrc1\_EXTRA2 | `10:11` | extra bits for Rsrc1 (R\*\_EXTRA2 Encoding) | -| Rsrc2\_EXTRA2 | `12:13` | extra bits for Rsrc2 (R\*\_EXTRA2 Encoding) | -| Rsrc3\_EXTRA2 | `14:15` | extra bits for Rsrc3 (R\*\_EXTRA2 Encoding| -| reserved | `16` | reserved | -| MODE | `19:23` | changes Vector behaviour | +| Field Name | Field bits | Description | +|------------|------------|----------------------------------------| +| MASK\_KIND | `0` | Execution Mask Kind | +| MASK | `1:3` | Execution Mask | +| ELWIDTH | `4:5` | Element Width | +| SUBVL | `6:7` | Sub-vector length | +| Rdest\_EXTRA2 | `8:9` | extends Rdest (R\*\_EXTRA2 Encoding) | +| Rsrc1\_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding) | +| Rsrc2\_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding) | +| Rsrc3\_EXTRA2 | `14:15` | extends Rsrc3 (R\*\_EXTRA2 Encoding) | +| reserved | `16` | reserved | +| MODE | `19:23` | changes Vector behaviour | ## RM-1P-2S1D -| Field Name | Field bits | Description | -|------------|------------|------------------------------------------------| -| MASK\_KIND | `0` | Execution Mask Kind | -| MASK | `1:3` | Execution Mask | -| ELWIDTH | `4:5` | Element Width | -| SUBVL | `6:7` | Sub-vector length | -| Rdest\_EXTRA3 | `8:10` | extra bits for Rdest (Uses R\*\_EXTRA3 Encoding) | -| Rsrc1\_EXTRA3 | `11:13` | extra bits for Rsrc1 (Uses R\*\_EXTRA3 Encoding) | -| Rsrc2\_EXTRA3 | `14:16` | extra bits for Rsrc3 (Uses R\*\_EXTRA3 Encoding) | -| MODE | `19:23` | changes Vector behaviour | +| Field Name | Field bits | Description | +|------------|------------|-------------------------------------------| +| MASK\_KIND | `0` | Execution Mask Kind | +| MASK | `1:3` | Execution Mask | +| ELWIDTH | `4:5` | Element Width | +| SUBVL | `6:7` | Sub-vector length | +| Rdest\_EXTRA3 | `8:10` | extends Rdest (Uses R\*\_EXTRA3 Encoding) | +| Rsrc1\_EXTRA3 | `11:13` | extends Rsrc1 (Uses R\*\_EXTRA3 Encoding) | +| Rsrc2\_EXTRA3 | `14:16` | extends Rsrc3 (Uses R\*\_EXTRA3 Encoding) | +| MODE | `19:23` | changes Vector behaviour | These are for 2 operand 1 dest instructions, such as `add RT, RA, RB`. However also included are unusual instructions with the same src @@ -157,8 +157,8 @@ augmented to 7 bits in length. | MASK | `1:3` | Execution Mask | | ELWIDTH | `4:5` | Element Width | | SUBVL | `6:7` | Sub-vector length | -| Rdest_EXTRA3 | `8:10` | extra bits for Rdest | -| Rsrc1_EXTRA3 | `11:13` | extra bits for Rsrc1 | +| Rdest_EXTRA3 | `8:10` | extends Rdest | +| Rsrc1_EXTRA3 | `11:13` | extends Rsrc1 | | MASK_SRC | `14:16` | Execution Mask for Source | | ELWIDTH_SRC | `17:18` | Element Width for Source | | MODE | `19:23` | changes Vector behaviour | @@ -180,9 +180,9 @@ RM-2P-2S1D: | MASK | `1:3` | Execution Mask | | ELWIDTH | `4:5` | Element Width | | SUBVL | `6:7` | Sub-vector length | -| Rdest_EXTRA2 | `8:9` | extra bits for Rdest (R\*\_EXTRA2 Encoding) | -| Rsrc1_EXTRA2 | `10:11` | extra bits for Rsrc1 (R\*\_EXTRA2 Encoding) | -| Rsrc2_EXTRA2 | `12:13` | extra bits for Rsrc2 (R\*\_EXTRA2 Encoding) | +| Rdest_EXTRA2 | `8:9` | extends Rdest (R\*\_EXTRA2 Encoding) | +| Rsrc1_EXTRA2 | `10:11` | extends Rsrc1 (R\*\_EXTRA2 Encoding) | +| Rsrc2_EXTRA2 | `12:13` | extends Rsrc2 (R\*\_EXTRA2 Encoding) | | MASK_SRC | `14:16` | Execution Mask for Source | | ELWIDTH_SRC | `17:18` | Element Width for Source | | MODE | `19:23` | changes Vector behaviour |