From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 16 Feb 2022 13:16:10 +0000 (+0000)
Subject: wildcards never ok. update comments
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e3b44dac296745fc20601f179179f27ab3d3a148;p=ls2.git

wildcards never ok. update comments
---

diff --git a/src/crg.py b/src/crg.py
index 195e8fd..3cf483f 100644
--- a/src/crg.py
+++ b/src/crg.py
@@ -10,7 +10,8 @@
 # under EU Grants 871528 and 957073, under the LGPLv3+ License
 
 
-from nmigen import *
+from nmigen import (Elaboratable, Module, Signal, ClockDomain, Instance,
+                    ClockSignal, ResetSignal)
 
 __ALL__ = ["ECPIX5CRG"]
 
@@ -110,6 +111,7 @@ class PLL(Elaboratable):
             i_CLKI          = self.clkin,
             o_LOCK          = self.locked,
         )
+        # for each clock-out, set additional parameters
         for n, (clk, f, p, m) in sorted(self.clkouts.items()):
             n_to_l = {0: "P", 1: "S", 2: "S2"}
             div    = config["clko{}_div".format(n)]