From: lkcl <lkcl@web>
Date: Sun, 3 Oct 2021 00:41:53 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3737
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e3bdddf027cfa09c1c7ce616ab0ec2b9a29dd30e;p=libreriscv.git

---

diff --git a/3d_gpu/architecture/dynamic_simd.mdwn b/3d_gpu/architecture/dynamic_simd.mdwn
index b86fd00fa..b840540ac 100644
--- a/3d_gpu/architecture/dynamic_simd.mdwn
+++ b/3d_gpu/architecture/dynamic_simd.mdwn
@@ -175,6 +175,7 @@ basic HDL is literally an order of magnitude larger:
 To save hugely on gate count the normal practice of having separate scalar ALUs and separate SIMD ALUs is not followed.
 
 Instead a suite of "partition points" identical in fashion to the Aspex Microelectronics ASP (Array-String-Architecture) architecture is deployed.
+These "breaks" may be set at runtime at any time.
 
 Basic principle: when all partition gates are open the ALU is subdivided into isolated and independent 8 bit SIMD ALUs.  Whenever any one gate is opened, the relevant 8 bit "part-results" are chained together in a downstream cascade to create 16 bit, 32 bit, 64 bit and 128 bit compound results.