From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 30 May 2019 19:26:51 +0000 (-0700)
Subject: Do not re-sort box_module ports
X-Git-Tag: working-ls180~1208^2~232
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e3c8132d7acaae328adeb8d4db1857275b5e8323;p=yosys.git

Do not re-sort box_module ports
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 25de7daba..efdd1844b 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -739,10 +739,12 @@ struct XAigerWriter
 				if (box_module->get_bool_attribute("\\whitebox"))
 					holes_cell = holes_module->addCell(cell->name, cell->type);
 
-				RTLIL::Wire *holes_wire;
-				// TODO: Only sort once
-				box_module->wires_.sort(RTLIL::sort_by_id_str());
-				for (const auto w : box_module->wires()) {
+				// NB: Assume box_module->ports are sorted alphabetically
+				//     (as RTLIL::Module::fixup_ports() would do)
+				for (const auto &port_name : box_module->ports) {
+					RTLIL::Wire *w = box_module->wire(port_name);
+					log_assert(w);
+					RTLIL::Wire *holes_wire;
 					RTLIL::SigSpec port_wire;
 					if (w->port_input) {
 						for (int i = 0; i < GetSize(w); i++) {