From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 22 Aug 2020 23:46:00 +0000 (+0100)
Subject: load bios not 1.bin unit test
X-Git-Tag: semi_working_ecp5~272^2~19
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e3d0ca43c7fac19e58a649733d5165eeb5a34411;p=soc.git

load bios not 1.bin unit test
---

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index 4699ac6d..68be7702 100755
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -50,6 +50,7 @@ class LibreSoCSim(SoCSDRAM):
         #            "hello_world/hello_world.bin"
         ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
                     "tests/1.bin"
+        ram_fname = None
 
         ram_init = []
         if ram_fname: