From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 3 Dec 2021 14:22:43 +0000 (+0000)
Subject: add link to exceptions in gtkw traces
X-Git-Tag: sv_maxu_works-initial~670
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e3ebbf0867200bb9934188e6b569136e4e2e2f9e;p=openpower-isa.git

add link to exceptions in gtkw traces
---

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index 550d7eb2..089ac4f7 100644
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -387,7 +387,14 @@ class TestRunnerBase(FHDLTestCase):
             'core.int.rp_src1.memory(7)[63:0]',
             'core.int.rp_src1.memory(9)[63:0]',
             'core.int.rp_src1.memory(10)[63:0]',
-            'core.int.rp_src1.memory(13)[63:0]'
+            'core.int.rp_src1.memory(13)[63:0]',
+            # Exceptions: see list archive for description of the chain
+            # http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-December/004220.html
+            ('exceptions', 'closed', [
+                'exc_happened',
+                'pdecode2.exc_happened',
+                'core.exc_happened',
+                'core.fus.ldst0.exc_o_happened']),
         ]
 
         # PortInterface module path varies depending on MMU option