From: Clifford Wolf Date: Wed, 22 May 2019 11:56:56 +0000 (+0200) Subject: Keep zero-width wires in opt_clean if and only if they are ports, fixes #1023 X-Git-Tag: yosys-0.9~107^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e3f9ccf56d65ba72dfa625e9716d1182f36a381e;p=yosys.git Keep zero-width wires in opt_clean if and only if they are ports, fixes #1023 Signed-off-by: Clifford Wolf --- diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index bf8020169..7011d4602 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -319,8 +319,9 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos wire->attributes.erase("\\init"); if (GetSize(wire) == 0) { - // delete zero-width wires - goto delete_this_wire; + // delete zero-width wires, unless they are module ports + if (wire->port_id == 0) + goto delete_this_wire; } else if (wire->port_id != 0 || wire->get_bool_attribute("\\keep") || !initval.is_fully_undef()) { // do not delete anything with "keep" or module ports or initialized wires