From: Dave Airlie <airlied@redhat.com>
Date: Fri, 9 Nov 2018 02:13:17 +0000 (+1000)
Subject: iris: iris add load register reg32/64
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e4115eaca015ad97e1668a9237a3896326074a4d;p=mesa.git

iris: iris add load register reg32/64

These will be needed for broadwell and conditional render
---

diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h
index 6f0526db55f..6cb07119efe 100644
--- a/src/gallium/drivers/iris/iris_context.h
+++ b/src/gallium/drivers/iris/iris_context.h
@@ -308,6 +308,10 @@ struct iris_vtable {
    void (*upload_compute_state)(struct iris_context *ice,
                                 struct iris_batch *batch,
                                 const struct pipe_grid_info *grid);
+   void (*load_register_reg32)(struct iris_batch *batch, uint32_t src,
+                               uint32_t dst);
+   void (*load_register_reg64)(struct iris_batch *batch, uint32_t src,
+                               uint32_t dst);
    void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg,
                                uint32_t val);
    void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg,
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 675037a5162..ba7c98a6fd2 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -485,6 +485,15 @@ _iris_emit_lri(struct iris_batch *batch, uint32_t reg, uint32_t val)
 }
 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
 
+static void
+_iris_emit_lrr(struct iris_batch *batch, uint32_t src, uint32_t dst)
+{
+   iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_REG), lrr) {
+      lrr.SourceRegisterAddress = src;
+      lrr.DestinationRegisterAddress = dst;
+   }
+}
+
 static void
 emit_pipeline_select(struct iris_batch *batch, uint32_t pipeline)
 {
@@ -4745,6 +4754,21 @@ iris_destroy_state(struct iris_context *ice)
 
 /* ------------------------------------------------------------------- */
 
+static void
+iris_load_register_reg32(struct iris_batch *batch, uint32_t src,
+                         uint32_t dst)
+{
+   _iris_emit_lrr(batch, src, dst);
+}
+
+static void
+iris_load_register_reg64(struct iris_batch *batch, uint32_t src,
+                         uint32_t dst)
+{
+   _iris_emit_lrr(batch, src, dst);
+   _iris_emit_lrr(batch, src + 4, dst + 4);
+}
+
 static void
 iris_load_register_imm32(struct iris_batch *batch, uint32_t reg,
                          uint32_t val)
@@ -5322,6 +5346,8 @@ genX(init_state)(struct iris_context *ice)
    ice->vtbl.update_surface_base_address = iris_update_surface_base_address;
    ice->vtbl.upload_compute_state = iris_upload_compute_state;
    ice->vtbl.emit_raw_pipe_control = iris_emit_raw_pipe_control;
+   ice->vtbl.load_register_reg32 = iris_load_register_reg32;
+   ice->vtbl.load_register_reg64 = iris_load_register_reg64;
    ice->vtbl.load_register_imm32 = iris_load_register_imm32;
    ice->vtbl.load_register_imm64 = iris_load_register_imm64;
    ice->vtbl.load_register_mem32 = iris_load_register_mem32;