From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 20 Feb 2021 12:23:04 +0000 (+0000)
Subject: add (unused) code for writing out SVSTATE in TestIssuer
X-Git-Tag: convert-csv-opcode-to-binary~206
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e4327f3fe04f1ff2fee29683c9ce478b691b1e43;p=soc.git

add (unused) code for writing out SVSTATE in TestIssuer
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 782bded6..1298e4ae 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -39,6 +39,7 @@ from soc.interrupts.xics import XICS_ICP, XICS_ICS
 from soc.bus.simple_gpio import SimpleGPIO
 from soc.clock.select import ClockSelect
 from soc.clock.dummypll import DummyPLL
+from soc.sv.svstate import SVSTATERec
 
 
 from nmutil.util import rising_edge
@@ -407,6 +408,14 @@ class TestIssuerInternal(Elaboratable):
                     sync += core.bigendian_i.eq(0)
                     m.next = "INSN_FETCH"  # back to fetch
 
+        # for updating svstate (things like srcstep etc.)
+        update_svstate = Signal() # TODO: move this somewhere above
+        new_svstate = SVSSTATERec("new_svstate") # and move this as well
+        # check if svstate needs updating: if so, write it to State Regfile
+        with m.If(update_svstate):
+            comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
+            comb += self.state_w_sv.data_i.eq(new_svstate)
+
         # this bit doesn't have to be in the FSM: connect up to read
         # regfiles on demand from DMI
         with m.If(d_reg.req): # request for regfile access being made