From: lkcl <lkcl@web>
Date: Fri, 10 Jun 2022 05:48:59 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1882
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e4425c85511c59f2f01b5111bdc1f36370a4fa87;p=libreriscv.git

---

diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn
index 0566c6f25..6a838b089 100644
--- a/openpower/sv/mv.swizzle.mdwn
+++ b/openpower/sv/mv.swizzle.mdwn
@@ -29,7 +29,7 @@ this gives a 12 bit immediate across bits 16 to 25 and 29-30.
 
 except that the options are:
 
-* 0b0NN index 0 thru 3 to place subelement in pos XYZW
+* 0b0NN index 0 thru 3 to copy from subelement in pos XYZW
 * 0b110 to indicate "skip".  this is equivalent to predicate masking
 * 0b100 to indicate "constant 0"
 * 0b101 to indicate "constant 1" (or 1.0)
@@ -38,5 +38,7 @@ except that the options are:
 Evaluating efforts to encode 12 bit swizzle into less proved unsuccessful: 7^4 comes out to 2,400 which is larger than 11 bits.
 
 Note that 7 options are needed (not 6) because the 7th option allows predicate masking to be encoded within the swizzle immediate.
+For example this allows "W..Y" to be specified, "copy W to position X,
+and Y to position W, leave the other two positions Y and Z unaltered"
 
 Mode M is described in [[mv.vec]] and allows for merge and split of vectors.