From: Jacob Lifshay Date: Thu, 29 Sep 2022 23:21:22 +0000 (-0700) Subject: convert svp64 bigint unittests to use TestAccumulatorBase X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e45b267f404f95d007bc189d39e1b0e703ff2f8f;p=openpower-isa.git convert svp64 bigint unittests to use TestAccumulatorBase --- diff --git a/src/openpower/decoder/isa/test_caller_svp64_bigint.py b/src/openpower/decoder/isa/test_caller_svp64_bigint.py index 6f6f6dea..45973e43 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_bigint.py +++ b/src/openpower/decoder/isa/test_caller_svp64_bigint.py @@ -1,179 +1,21 @@ -from nmigen import Module, Signal -from nmigen.sim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase -import unittest -from openpower.decoder.isa.caller import ISACaller -from openpower.decoder.power_decoder import (create_pdecode) -from openpower.decoder.power_decoder2 import (PowerDecode2) -from openpower.simulator.program import Program -from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields -from openpower.decoder.selectable_int import SelectableInt -from openpower.decoder.orderedset import OrderedSet -from openpower.decoder.isa.all import ISA -from openpower.decoder.isa.test_caller import Register, run_tst -from openpower.sv.trans.svp64 import SVP64Asm -from openpower.consts import SVP64CROffs -from copy import deepcopy - -class DecoderTestCase(FHDLTestCase): - - def _check_regs(self, sim, expected): - for i in range(32): - self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64), - "reg %d expected %x got %x" % \ - (i, sim.gpr(i).value, expected[i])) - - def test_sv_bigint_add(self): - """performs a carry-rollover-vector-add aka "big integer vector add" - this is remarkably simple, each sv.adde uses and produces a CA which - goes into the next sv.adde. arbitrary size is possible (1024+) as - is looping using the CA bit from one sv.adde on another batch to do - unlimited-size biginteger add. - - r3/r2: 0x0000_0000_0000_0001 0xffff_ffff_ffff_ffff + - r5/r4: 0x8000_0000_0000_0000 0x0000_0000_0000_0001 = - r1/r0: 0x8000_0000_0000_0002 0x0000_0000_0000_0000 - """ - isa = SVP64Asm(['sv.adde *0, *2, *4' - ]) - lst = list(isa) - print ("listing", lst) - - # initial values in GPR regfile - initial_regs = [0] * 32 - initial_regs[2] = 0xffff_ffff_ffff_ffff # lo dword A - initial_regs[3] = 0x0000_0000_0000_0001 # hi dword A - initial_regs[4] = 0x0000_0000_0000_0001 # lo dword B - initial_regs[5] = 0x8000_0000_0000_0000 # hi dword B - # SVSTATE (in this case, VL=2) - svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) - # copy before running - expected_regs = deepcopy(initial_regs) - expected_regs[0] = 0x0 # rollover to zero, carry - expected_regs[1] = 0x8000_0000_0000_0002 # carry rolled-over - - with Program(lst, bigendian=False) as program: - sim = self.run_tst_program(program, initial_regs, svstate) - self._check_regs(sim, expected_regs) - - def test_sv_bigint_scalar_shiftright(self): - """performs a scalar-to-vector right-shift. +""" svp64 bigint tests +""" - r3 r2 r1 r4 - 0x0000_0000_0000_0002 0x8000_8000_8000_8001 0xffff_ffff_ffff_ffff >> 4 - 0x0000_0000_0000_0002 0x2800_0800_0800_0800 0x1fff_ffff_ffff_ffff - """ - isa = SVP64Asm(['sv.dsrd *0,*1,4,1' - ]) - lst = list(isa) - print ("listing", lst) - - # initial values in GPR regfile - initial_regs = [0] * 32 - initial_regs[0] = 0xffff_ffff_ffff_ffff # lo dword A - initial_regs[1] = 0x8000_8000_8000_8001 # mid dword A - initial_regs[2] = 0x0000_0000_0000_0002 # hi dword A - initial_regs[4] = 0x0000_0000_0000_0004 # shift amount (a nibble) - # SVSTATE (in this case, VL=2) - svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) - # copy before running - expected_regs = deepcopy(initial_regs) - expected_regs[0] = 0x1fff_ffff_ffff_ffff # MSB nibble gets LSB - expected_regs[1] = 0x2800_0800_0800_0800 # hi dword A - - with Program(lst, bigendian=False) as program: - sim = self.run_tst_program(program, initial_regs, svstate) - self._check_regs(sim, expected_regs) - - def test_sv_bigint_scalar_shiftleft(self): - """performs a scalar-to-vector left-shift: because the result is moved - down by one scalar (RT=0 not 1) there is no need for reverse-gear. - r2 is *not* modified (contains its original value). - r2 r1 r0 r4 - 0x0000_0000_0001_0002 0x3fff_ffff_ffff_ffff 0x4000_0000_0000_0001 << 4 - 0x0000_0000_0001_0002 0x0000_0000_0010_0023 0xffff_ffff_ffff_fff4 - """ - isa = SVP64Asm(['sv.dsld *0,*1,4,1' - ]) - lst = list(isa) - print ("listing", lst) - - # initial values in GPR regfile - initial_regs = [0] * 32 - initial_regs[0] = 0x4000_0000_0000_0001 # lo dword A - initial_regs[1] = 0x3fff_ffff_ffff_ffff # mid dword A - initial_regs[2] = 0x0000_0000_0001_0002 # hi dword A - initial_regs[4] = 0x0000_0000_0000_0004 # shift amount (a nibble) - # SVSTATE (in this case, VL=2) - svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 2 # MAXVL - print ("SVSTATE", bin(svstate.asint())) - # copy before running - expected_regs = deepcopy(initial_regs) - expected_regs[0] = 0xffff_ffff_ffff_fff4 # MSB nibble gets LSB - expected_regs[1] = 0x0000_0000_0010_0023 # hi dword A - - with Program(lst, bigendian=False) as program: - sim = self.run_tst_program(program, initial_regs, svstate) - self._check_regs(sim, expected_regs) - - def test_sv_bigint_mul(self): - """performs a carry-rollover-vector-mul-with-add with a scalar, - using "RC" as a 64-bit carry - - r1 r0 - 0xffff_ffff_ffff_ffff 0xffff_ffff_ffff_ffff * - r4 (scalar) 0xffff_ffff_ffff_fffe + - r10 (scalar-add-in) 0x0000_0000_0000_0100 + +import unittest +from openpower.test.runner import TestRunnerBase +from openpower.test.bigint.bigint_cases import SVP64BigIntCases - 0xffff_ffff_ffff_fffd 0xffff_ffff_ffff_ffff 0x0000_0000_0000_0102 - r10 (RC, MSB) r9 r8 - """ - isa = SVP64Asm(['sv.maddedu *8, *0, 4, 10' - ]) - lst = list(isa) - print ("listing", lst) +# writing the test_caller invocation this way makes it work with pytest - # initial values in GPR regfile - initial_regs = [0] * 32 - initial_regs[0] = 0xffff_ffff_ffff_ffff # lo dword of Vector A - initial_regs[1] = 0xffff_ffff_ffff_ffff # hi dword of Vector A - initial_regs[4] = 0xffff_ffff_ffff_fffe # scalar B - initial_regs[10] = 0x0000_0000_0000_0100 # RC-input - # SVSTATE (in this case, VL=2) - svstate = SVP64State() - svstate.vl = 2 # VL - svstate.maxvl = 3 # MAXVL - print ("SVSTATE", bin(svstate.asint())) - # copy before running - expected_regs = deepcopy(initial_regs) - # XXX the result is *three*-dword-long. RC, the carry roll-over, - # is a *legitimate* (valid) part of the result as it contains the - # hi-64-bit of the last multiply. - expected_regs[8] = 0x0000_0000_0000_0102 # least dword - expected_regs[9] = 0xffff_ffff_ffff_ffff # next dword - expected_regs[10] = 0xffff_ffff_ffff_fffd # carry roll-over, top dword - with Program(lst, bigendian=False) as program: - sim = self.run_tst_program(program, initial_regs, svstate) - self._check_regs(sim, expected_regs) +class TestSVP64BigInt(TestRunnerBase): + def __init__(self, test): + assert test == 'test' + super().__init__(SVP64BigIntCases().test_data) - def run_tst_program(self, prog, initial_regs=None, - svstate=None, - initial_cr=0): - if initial_regs is None: - initial_regs = [0] * 32 - simulator = run_tst(prog, initial_regs, svstate=svstate, - initial_cr=initial_cr) - simulator.gpr.dump() - return simulator + def test(self): + # dummy function to make unittest try to test this class + pass if __name__ == "__main__": diff --git a/src/openpower/test/bigint/bigint_cases.py b/src/openpower/test/bigint/bigint_cases.py index a783551c..2f1fae33 100644 --- a/src/openpower/test/bigint/bigint_cases.py +++ b/src/openpower/test/bigint/bigint_cases.py @@ -2,6 +2,7 @@ from openpower.test.common import TestAccumulatorBase, skip_case from openpower.sv.trans.svp64 import SVP64Asm from openpower.test.state import ExpectedState from openpower.simulator.program import Program +from openpower.decoder.isa.caller import SVP64State _SHIFT_TEST_RANGE = range(-64, 128, 16) @@ -143,3 +144,112 @@ class BigIntCases(TestAccumulatorBase): v >>= sh % 64 e.intregs[3] = v % 2 ** 64 self.add_case(prog, gprs, expected=e) + + +class SVP64BigIntCases(TestAccumulatorBase): + def case_sv_bigint_add(self): + """performs a carry-rollover-vector-add aka "big integer vector add" + this is remarkably simple, each sv.adde uses and produces a CA which + goes into the next sv.adde. arbitrary size is possible (1024+) as + is looping using the CA bit from one sv.adde on another batch to do + unlimited-size biginteger add. + + r19/r18: 0x0000_0000_0000_0001 0xffff_ffff_ffff_ffff + + r21/r20: 0x8000_0000_0000_0000 0x0000_0000_0000_0001 = + r17/r16: 0x8000_0000_0000_0002 0x0000_0000_0000_0000 + """ + prog = Program(list(SVP64Asm(["sv.adde *16, *18, *20"])), False) + gprs = [0] * 32 + gprs[18] = 0xffff_ffff_ffff_ffff + gprs[19] = 0x0000_0000_0000_0001 + gprs[20] = 0x0000_0000_0000_0001 + gprs[21] = 0x8000_0000_0000_0000 + svstate = SVP64State() + svstate.vl = 2 + svstate.maxvl = 2 + e = ExpectedState(pc=8, int_regs=gprs) + e.intregs[16] = 0x0000_0000_0000_0000 + e.intregs[17] = 0x8000_0000_0000_0002 + self.add_case(prog, gprs, expected=e, initial_svstate=svstate) + + def test_sv_bigint_shift_right_by_scalar(self): + """performs a bigint shift-right by scalar. + + r18 r17 r16 r3 + 0x0000_0000_5000_0002 0x8000_8000_8000_8001 0xffff_ffff_ffff_ffff >> 4 + 0x0000_0000_0500_0000 0x2800_0800_0800_0800 0x1fff_ffff_ffff_ffff + """ + prog = Program(list(SVP64Asm(["sv.dsrd *16,*17,3,1"])), False) + gprs = [0] * 32 + gprs[16] = 0xffff_ffff_ffff_ffff + gprs[17] = 0x8000_8000_8000_8001 + gprs[18] = 0x0000_0000_5000_0002 + gprs[3] = 4 + svstate = SVP64State() + svstate.vl = 3 + svstate.maxvl = 3 + e = ExpectedState(pc=8, int_regs=gprs) + e.intregs[16] = 0x1fff_ffff_ffff_ffff + e.intregs[17] = 0x2800_0800_0800_0800 + e.intregs[18] = 0x0000_0000_0500_0000 + self.add_case(prog, gprs, expected=e, initial_svstate=svstate) + + def test_sv_bigint_shift_left_by_scalar(self): + """performs a bigint shift-left by scalar. + + because the result is moved down by one register there is no need + for reverse-gear. + + r18 is *not* modified (contains its original value). + r18 r17 r16 r3 + 0x0000_0000_0001_0002 0x3fff_ffff_ffff_ffff 0x4000_0000_0000_0001 << 4 + r17 r16 r15 + 0x0000_0000_0010_0023 0xffff_ffff_ffff_fff4 0x0000_0000_0000_0010 + """ + prog = Program(list(SVP64Asm(["sv.dsld *15,*16,3,1"])), False) + gprs = [0] * 32 + gprs[15] = 0 + gprs[16] = 0x4000_0000_0000_0001 + gprs[17] = 0x3fff_ffff_ffff_ffff + gprs[18] = 0x0000_0000_0001_0002 + gprs[3] = 4 + svstate = SVP64State() + svstate.vl = 3 + svstate.maxvl = 3 + e = ExpectedState(pc=8, int_regs=gprs) + e.intregs[15] = 0x0000_0000_0000_0010 + e.intregs[16] = 0xffff_ffff_ffff_fff4 + e.intregs[17] = 0x0000_0000_0010_0023 + self.add_case(prog, gprs, expected=e, initial_svstate=svstate) + + def test_sv_bigint_mul_by_scalar(self): + """performs a carry-rollover-vector-mul-with-add with a scalar, + using "RC" as a 64-bit carry + + r18 r17 r16 + 0x1234_0000_5678_0000 0x9ABC_0000_DEF0_0000 0x1357_0000_9BDF_0000 * + r3 (scalar factor) + 0x1_0001 + + r4 (carry in) + r10 (scalar-add-in) 0xFEDC = + r18 r17 r16 + 0x1234_5678_5678_9ABC 0x9ABC_DEF0_DEF0_1357 0x1357_9BDF_9BDF_FEDC + r4 (carry out) + 0x1234 + """ + prog = Program(list(SVP64Asm(["sv.maddedu *16,*16,3,4"])), False) + gprs = [0] * 32 + gprs[16] = 0x1357_0000_9BDF_0000 + gprs[17] = 0x9ABC_0000_DEF0_0000 + gprs[18] = 0x1234_0000_5678_0000 + gprs[3] = 0x1_0001 + gprs[4] = 0xFEDC + svstate = SVP64State() + svstate.vl = 3 + svstate.maxvl = 3 + e = ExpectedState(pc=8, int_regs=gprs) + e.intregs[16] = 0x1357_9BDF_9BDF_FEDC + e.intregs[17] = 0x9ABC_DEF0_DEF0_1357 + e.intregs[18] = 0x1234_5678_5678_9ABC + e.intregs[4] = 0x1234 + self.add_case(prog, gprs, expected=e, initial_svstate=svstate)