From: Luke Kenneth Casson Leighton Date: Mon, 13 May 2019 07:38:58 +0000 (+0100) Subject: make read/write-pending syncd X-Git-Tag: div_pipeline~2060 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e45c9e2c6eecbd61c6ee2ae29cef4e937a463755;p=soc.git make read/write-pending syncd --- diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py index d40a34dd..220885f2 100644 --- a/src/experiment/score6600.py +++ b/src/experiment/score6600.py @@ -129,13 +129,13 @@ class FunctionUnits(Elaboratable): m.submodules.g_int_rd_pend_v = g_int_rd_pend_v m.submodules.g_int_wr_pend_v = g_int_wr_pend_v - m.d.comb += self.g_int_rd_pend_o.eq(g_int_rd_pend_v.g_pend_o) - m.d.comb += self.g_int_wr_pend_o.eq(g_int_wr_pend_v.g_pend_o) + m.d.sync += self.g_int_rd_pend_o.eq(g_int_rd_pend_v.g_pend_o) + m.d.sync += self.g_int_wr_pend_o.eq(g_int_wr_pend_v.g_pend_o) # Connect INT Fn Unit global wr/rd pending for fu in if_l: - m.d.comb += fu.g_int_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o) - m.d.comb += fu.g_int_rd_pend_i.eq(g_int_rd_pend_v.g_pend_o) + m.d.comb += fu.g_int_wr_pend_i.eq(self.g_int_wr_pend_o) + m.d.comb += fu.g_int_rd_pend_i.eq(self.g_int_rd_pend_o) # Connect function issue / busy arrays, and dest/src1/src2 fn_busy_l = []