From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 25 Mar 2015 08:00:41 +0000 (+0100)
Subject: Fixes in cmos_cells.v
X-Git-Tag: yosys-0.6~370
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e468d4cc6001b65b9c7e72d3f9c0e9b939ad31b9;p=yosys.git

Fixes in cmos_cells.v
---

diff --git a/techlibs/cmos/cmos_cells.v b/techlibs/cmos/cmos_cells.v
index da75270cb..27278facb 100644
--- a/techlibs/cmos/cmos_cells.v
+++ b/techlibs/cmos/cmos_cells.v
@@ -1,17 +1,26 @@
 
+module BUF(A, Y);
+input A;
+output Y;
+assign Y = A;
+endmodule
+
 module NOT(A, Y);
 input A;
-output Y = ~A;
+output Y;
+assign Y = ~A;
 endmodule
 
 module NAND(A, B, Y);
 input A, B;
-output Y = ~(A & B);
+output Y;
+assign Y = ~(A & B);
 endmodule
 
 module NOR(A, B, Y);
 input A, B;
-output Y = ~(A | B);
+output Y;
+assign Y = ~(A | B);
 endmodule
 
 module DFF(C, D, Q);