From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 17 Jun 2019 07:20:21 +0000 (+0200)
Subject: targets/ulx3s: use CAS latency of 3 to be compatible with production boards
X-Git-Tag: 24jan2021_ls180~1163
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e46d287b64b181d12caa2de8782d41c462dfcacd;p=litex.git

targets/ulx3s: use CAS latency of 3 to be compatible with production boards
---

diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py
index 40503bad..f3a3aac0 100755
--- a/litex/boards/targets/ulx3s.py
+++ b/litex/boards/targets/ulx3s.py
@@ -59,7 +59,7 @@ class BaseSoC(SoCSDRAM):
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
         if not self.integrated_main_ram_size:
-            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
+            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=3)
             sdram_module = MT48LC16M16(sys_clk_freq, "1:1")
             self.register_sdram(self.sdrphy,
                                 sdram_module.geom_settings,