From: lkcl <lkcl@web>
Date: Tue, 7 Jun 2022 16:02:27 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1921
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e4700340baa8c0f11f8704d6a10920c0e4cc381f;p=libreriscv.git

---

diff --git a/openpower/sv/compliancy_levels.mdwn b/openpower/sv/compliancy_levels.mdwn
index c9b820622..47fd91076 100644
--- a/openpower/sv/compliancy_levels.mdwn
+++ b/openpower/sv/compliancy_levels.mdwn
@@ -21,6 +21,12 @@ Summary of Compliancy Levels, each Level includes all lower levels:
 
 * **Ultra-embedded**: `setvl` instruction and context-switching of SVSTATE
   into SVSRR1. Register Files as Standard Power ISA.
-* **Embedded**: `svstep` instruction, all SV Branch instructions,
+* **Embedded**: `svstep` instruction,
   and support for Hardware for-looping
   in both Horizontal-First and Vertical-First Mode as well as Predication
+  (Single and Twin)
+* **DSP/VPU**: 128 registers, all SV Branch instructions,
+  crweird instructions, element-width
+  overrides, and all Modes (Saturation, Fail-First, Predicate-Result,
+  Mapreduce/Iteration)
+* **3D/Advanced/Supercomputing**: REMAP capability