From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 13 Feb 2020 07:34:16 +0000 (+0100)
Subject: soc_core: fix cpu_variant renaming regression
X-Git-Tag: 24jan2021_ls180~669
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e4712ff7f32020716a802ded776bea18aa53a092;p=litex.git

soc_core: fix cpu_variant renaming regression
---

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 8d4dd8a8..0d59924e 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -120,14 +120,14 @@ class SoCCore(LiteXSoC):
         self.config      = {}
 
         # Parameters management --------------------------------------------------------------------
-        if cpu_type == "None":
-            cpu_type = None
+        cpu_type    = None if cpu_type == "None" else cpu_type
+        cpu_variant = cpu.check_format_cpu_variant(cpu_variant)
 
         if not with_wishbone:
             self.mem_map["csr"]  = 0x00000000
 
         self.cpu_type                   = cpu_type
-        self.cpu_variant                = cpu.check_format_cpu_variant(cpu_variant)
+        self.cpu_variant                = cpu_variant
 
         self.integrated_rom_size        = integrated_rom_size
         self.integrated_rom_initialized = integrated_rom_init != []