From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 10 May 2015 19:23:59 +0000 (+0200)
Subject: Merge pull request #62 from wluker/verilog-backend-mem
X-Git-Tag: yosys-0.6~297
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e47218e9ea678b705cb79e687fa88d8afb2ced4e;p=yosys.git

Merge pull request #62 from wluker/verilog-backend-mem

Added support for $mem cells in the verilog backend.
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e47218e9ea678b705cb79e687fa88d8afb2ced4e