From: dh73 <dh73_fpga@qq.com>
Date: Sun, 1 Oct 2017 16:11:32 +0000 (-0500)
Subject: Fixed wrong declaration in Verilog backend
X-Git-Tag: yosys-0.8~307^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e4808477531d31284244188637af3ccf89a21269;p=yosys.git

Fixed wrong declaration in Verilog backend
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 33f9a81e4..48e06dc7c 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -175,7 +175,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 			if (set_signed && val < 0)
 				f << stringf("-32'sd%u", -val);
 			else {
-                                if(!nobasenradix)
+                                if(nobasenradix)
                                   f << stringf("%u", val); // There's no signed parameter on megawizard IP 
                                 else
                                        f << stringf("32'%sd%u", set_signed ? "s" : "", val);
@@ -1585,8 +1585,8 @@ struct VerilogBackend : public Backend {
 				continue;
 			}
                         if (arg == "-nobasenradix") {
-                          defparam = true;
-                          continue;
+                                nobasenradix = true;
+                                continue;
 			}
 			if (arg == "-blackboxes") {
 				blackboxes = true;