From: Luke Kenneth Casson Leighton Date: Tue, 7 Jul 2020 15:02:24 +0000 (+0100) Subject: debugging termination (OP_ATTN) X-Git-Tag: div_pipeline~162^2~8 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e4857e5f8b3d35964148ed840fafaa3376f456ec;p=soc.git debugging termination (OP_ATTN) --- diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 45b60fb9..4f814cf7 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -588,8 +588,11 @@ class PowerDecode2(Elaboratable): # set up instruction, pick fn unit comb += e.nia.eq(0) # XXX TODO (or remove? not sure yet) fu = op.function_unit - itype = Mux(fu == Function.NONE, InternalOp.OP_ILLEGAL, op.internal_op) - comb += do.insn_type.eq(itype) + with m.If((fu == Function.NONE) | + (op.internal_op == InternalOp.OP_ATTN)): + comb += do.insn_type.eq(op.internal_op) + with m.Else(): + comb += do.insn_type.eq(InternalOp.OP_ILLEGAL) comb += do.fn_unit.eq(fu) # registers a, b, c and out and out2 (LD/ST EA) diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index 6e2ab94c..69445548 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -149,7 +149,9 @@ def set_issue(core, dec2, sim): def wait_for_busy_clear(cu): while True: busy_o = yield cu.busy_o - if not busy_o: + terminated_o = yield cu.core_terminated_o + if not busy_o or terminated_o: + print("busy/terminated:", busy_o, terminated_o) break print("busy",) yield diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py index 8b80613b..e679fcd2 100644 --- a/src/soc/simple/test/test_issuer.py +++ b/src/soc/simple/test/test_issuer.py @@ -140,6 +140,9 @@ class TestRunner(FHDLTestCase): yield from wait_for_busy_hi(core) yield from wait_for_busy_clear(core) + terminated = yield core.core_terminated_o + print ("terminated", terminated) + print ("sim", code) # call simulated operation opname = code.split(' ')[0]