From: Clifford Wolf Date: Tue, 9 Jun 2015 07:54:22 +0000 (+0200) Subject: Added cellaigs API X-Git-Tag: yosys-0.6~268 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e49e2662aae12a1ff980a89b06e5b46403f6068d;p=yosys.git Added cellaigs API --- diff --git a/Makefile b/Makefile index fc3329c8e..c7626c70d 100644 --- a/Makefile +++ b/Makefile @@ -225,7 +225,7 @@ $(eval $(call add_include_file,libs/sha1/sha1.h)) $(eval $(call add_include_file,passes/fsm/fsmdata.h)) $(eval $(call add_include_file,backends/ilang/ilang_backend.h)) -OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o +OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/cellaigs.o kernel/log.o: CXXFLAGS += -DYOSYS_SRC='"$(YOSYS_SRC)"' OBJS += libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc new file mode 100644 index 000000000..735c86654 --- /dev/null +++ b/kernel/cellaigs.cc @@ -0,0 +1,123 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/cellaigs.h" + +YOSYS_NAMESPACE_BEGIN + +bool AigNode::operator==(const AigNode &other) const +{ + if (portname != other.portname) return false; + if (portbit != other.portbit) return false; + if (inverter != other.inverter) return false; + if (left_parent != other.left_parent) return false; + if (right_parent != other.right_parent) return false; + return true; +} + +unsigned int AigNode::hash() const +{ + unsigned int h = mkhash_init; + h = mkhash(portname.hash(), portbit); + h = mkhash(h, inverter); + h = mkhash(h, left_parent); + h = mkhash(h, right_parent); + return h; +} + +struct AigMaker +{ + Aig *aig; + idict aig_indices; + + AigMaker(Aig *aig) : aig(aig) { } + + int inport(IdString portname, int portbit, bool inverter = false) + { + AigNode node; + node.portname = portname; + node.portbit = portbit; + node.inverter = inverter; + node.left_parent = -1; + node.right_parent = -1; + + if (!aig_indices.count(node)) { + aig_indices.expect(node, GetSize(aig->nodes)); + aig->nodes.push_back(node); + } + + return aig_indices.at(node); + } + + int gate(int left_parent, int right_parent, bool inverter = false) + { + AigNode node; + node.portbit = -1; + node.inverter = inverter; + node.left_parent = left_parent; + node.right_parent = right_parent; + + if (!aig_indices.count(node)) { + aig_indices.expect(node, GetSize(aig->nodes)); + aig->nodes.push_back(node); + } + + return aig_indices.at(node); + } + + void outport(int node, IdString portname, int portbit) + { + aig->nodes.at(node).outports.push_back(pair(portname, portbit)); + } +}; + +Aig::Aig(Cell *cell) +{ + if (cell->type[0] != '$') + return; + + AigMaker mk(this); + name = cell->type.str(); + + cell->parameters.sort(); + for (auto p : cell->parameters) + name += stringf(":%d", p.second.as_int()); + + if (cell->type == "$_AND_" || cell->type == "$_NAND_") + { + int A = mk.inport("A", 0); + int B = mk.inport("B", 0); + int Y = mk.gate(A, B, cell->type == "$_NAND_"); + mk.outport(Y, "Y", 0); + return; + } + + if (cell->type == "$_OR_" || cell->type == "$_NOR_") + { + int A = mk.inport("A", 0, true); + int B = mk.inport("B", 0, true); + int Y = mk.gate(A, B, cell->type == "$_OR_"); + mk.outport(Y, "Y", 0); + return; + } + + name.clear(); +} + +YOSYS_NAMESPACE_END diff --git a/kernel/cellaigs.h b/kernel/cellaigs.h new file mode 100644 index 000000000..db635ba90 --- /dev/null +++ b/kernel/cellaigs.h @@ -0,0 +1,48 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef CELLAIGS_H +#define CELLAIGS_H + +#include "kernel/yosys.h" + +YOSYS_NAMESPACE_BEGIN + +struct AigNode +{ + IdString portname; + int portbit; + bool inverter; + int left_parent, right_parent; + vector> outports; + + bool operator==(const AigNode &other) const; + unsigned int hash() const; +}; + +struct Aig +{ + string name; + vector nodes; + Aig(Cell *cell); +}; + +YOSYS_NAMESPACE_END + +#endif diff --git a/kernel/hashlib.h b/kernel/hashlib.h index b6cedc496..bb7afd78d 100644 --- a/kernel/hashlib.h +++ b/kernel/hashlib.h @@ -30,7 +30,7 @@ inline unsigned int mkhash(unsigned int a, unsigned int b) { const unsigned int mkhash_init = 5381; // The ADD version of DJB2 -// (usunsigned int mkhashe this version for cache locality in b) +// (use this version for cache locality in b) inline unsigned int mkhash_add(unsigned int a, unsigned int b) { return ((a << 5) + a) + b; }