From: Alberto Gonzalez <boqwxp@airmail.cc>
Date: Fri, 10 Apr 2020 07:19:05 +0000 (+0000)
Subject: Do not modify design modules while iterating over `modules()`.
X-Git-Tag: working-ls180~517^2~26
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e49fdee40441cb4b1892007560d56467fd75a798;p=yosys.git

Do not modify design modules while iterating over `modules()`.

Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
---

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index f300c2f72..930b4c416 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -1423,11 +1423,14 @@ struct FlattenPass : public Pass {
 							new_used_modules.insert(cell->type);
 			}
 
+			std::set<RTLIL::Module *> to_remove;
 			for (auto mod : design->modules())
 				if (!used_modules[mod->name] && !mod->get_blackbox_attribute(worker.ignore_wb)) {
 					log("Deleting now unused module %s.\n", log_id(mod));
-					design->remove(mod);
+					to_remove.insert(mod);
 				}
+			for (auto mod : to_remove)
+				design->remove(mod);
 		}
 
 		log_pop();