From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 31 Jul 2019 22:45:15 +0000 (-0700)
Subject: Restore old CO behaviour
X-Git-Tag: working-ls180~1039^2~289
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e4a638c29297e3e8b915cf84a2dddc339f511476;p=yosys.git

Restore old CO behaviour
---

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 369cb211e..00794ca0d 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -144,14 +144,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	// SB_MAC16 Output Interface
 
 	SigSpec O = st.sigO;
-	if (GetSize(O) == 33) {
-		cell->setPort("\\CO", st.sigO[32]);
-		O.remove(32);
+	int O_width = GetSize(O);
+	if (O_width == 33) {
+		log_assert(st.addAB);
+		cell->setPort("\\CO", O[-1]);
+		O.remove(O_width-1);
 	}
-	else {
-		log_assert(GetSize(O) <= 32);
+	else
 		cell->setPort("\\CO", pm.module->addWire(NEW_ID));
-	}
+	log_assert(GetSize(O) <= 32);
 	if (GetSize(O) < 32)
 		O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));