From: Sebastien Bourdeauducq Date: Mon, 6 May 2013 12:21:39 +0000 (+0200) Subject: xilinx_ise: enable register balancing X-Git-Tag: 24jan2021_ls180~2099^2~443^2~35 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e4b0e8ed6d3397698913ab946c54437107830fd8;p=litex.git xilinx_ise: enable register balancing --- diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index 63e68bfc..85d27712 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -81,6 +81,7 @@ def _build_files(device, sources, named_sc, named_pc, build_name): -ifmt MIXED -opt_mode SPEED -reduce_control_sets auto +-register_balancing yes -ofn %s.ngc -p %s""" % (build_name, build_name, device) tools.write_to_file(build_name + ".xst", xst_contents)