From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 28 Jun 2019 09:23:05 +0000 (+0100)
Subject: sub-loop independent (only one offset)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e4d4716b662b24720ae39e7fc29301d5f70288b9;p=riscv-isa-sim.git

sub-loop independent (only one offset)
---

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index f249d7e..ce70574 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -178,26 +178,29 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
         fprintf(stderr, "pre twin reg %s src %d dest %d pred %lx %lx\n",
             xstr(INSN), *src_offs, *dest_offs, src_pred, dest_pred);
 #endif
-    if (!zeroingsrc)
+    if (inc_offs(vlen, subvl, *dest_subo))
     {
-      // skip over masked-out elements in the src reg
-      while ((src_pset = (src_pred & (1<<pred_remap(src_preg, *src_offs))))
-                        == 0) {
-          inc_offs(vlen, subvl, *src_offs, *src_subo);
-          if (*src_offs >= vlen) {
-              break;
-          }
+      if (!zeroingsrc)
+      {
+        // skip over masked-out elements in the src reg
+        while ((src_pset = (src_pred & (1<<pred_remap(src_preg, *src_offs))))
+                          == 0) {
+            (*src_offs) += 1;
+            if (*src_offs >= vlen) {
+                break;
+            }
+        }
       }
-    }
-    if (!zeroing)
-    {
-      // skip over masked-out elements in the dest reg
-      while ((dest_pset = (dest_pred & (1<<pred_remap(dest_preg, *dest_offs))))
-                        == 0) {
-          inc_offs(vlen, subvl, *dest_offs, *dest_subo);
-          if (*dest_offs >= vlen) {
-              break;
-          }
+      if (!zeroing)
+      {
+        // skip over masked-out elements in the dest reg
+        while ((dest_pset = (dest_pred & (1<<pred_remap(dest_preg, *dest_offs))))
+                          == 0) {
+            (*dest_offs) += 1;
+            if (*dest_offs >= vlen) {
+                break;
+            }
+        }
       }
     }
     if (*src_offs >= vlen || *dest_offs >= vlen) {
@@ -287,10 +290,12 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
       {
         break;
       }
+      if (inc_offs(vlen, subvl, *dest_subo)) {
 #ifdef INSN_CATEGORY_TWINPREDICATION
-      inc_offs(vlen, subvl, *src_offs, *src_subo);
+          (*src_offs) += 1;
 #endif
-      inc_offs(vlen, subvl, *dest_offs, *dest_subo);
+          (*dest_offs) += 1;
+      }
   } // end voffs loop
 #ifdef INSN_TYPE_BRANCH
   // ok, at the end of the loop, if the predicates are equal,
diff --git a/riscv/sv.cc b/riscv/sv.cc
index 66b494a..e5da9f3 100644
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -20,27 +20,21 @@ uint8_t maxelwidth(uint8_t wid1, uint8_t wid2)
     return std::max(wid1, wid2);
 }
 
-/* increments the offset and sub-offset appropriately in a FSM-based
+/* increments the sub-offset appropriately in a FSM-based
    version of a twin-nested for-loop:
-   for (offs = 0; offs < vlen; offs++) {
      for (suboffs = 0; suboffs < subvl; suboffs++) {
      ... doooo stuuuuff (python would use "yield" here)
      }
      suboffs = 0; // reset to zero after "loop"
-   }
 */
-bool inc_offs(int vlen, int subvl, int &offs, int &suboffs)
+bool inc_offs(int vlen, int subvl, int &suboffs)
 {
     suboffs++;
     if (suboffs < subvl) {
-        return true; // double-nested loop can continue
+        return false; // outer loop should not increment
     }
     suboffs = 0; // reset the sub-offs
-    offs += 1; // increment the outer (VL) loop instead
-    if (offs < vlen) {
-        return true; // also can continue
-    }
-    return false; // should not continue, however let FN deal with it
+    return true; // indicates outer (VL) loop should increment
 }
 
 sv_insn_t::sv_insn_t(processor_t *pr, bool _sv_enabled,
diff --git a/riscv/sv.h b/riscv/sv.h
index be96c8c..2a9cf4f 100644
--- a/riscv/sv.h
+++ b/riscv/sv.h
@@ -119,6 +119,6 @@ typedef struct {
 #define SV_CFG_BANK (0x7)
 #define SV_CFG_SIZE (0x3<<3)
 
-bool inc_offs(int vlen, int subvl, int &offs, int &suboffs);
+bool inc_offs(int vlen, int subvl, int &suboffs);
 
 #endif