From: Matt Turner Date: Tue, 1 Sep 2020 19:09:16 +0000 (-0700) Subject: intel/tools: Disassemble WAIT's argument as a destination X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e4dadb545fa6cdf52b5a6a7efb5764495e09158c;p=mesa.git intel/tools: Disassemble WAIT's argument as a destination WAIT takes a notification register as a destination and a src0 argument. Since the same notification register is specified in both fields, we treat it as a special case and disassemble it only once. If we disassemble it as if it is a source register, its scalar region will be printed as <0,1,0>. This causes difficulties round-tripping through the assembler <-> disassembler because that is not an acceptable destination region. If we instead disassemble the destination, we instead get a <1> region which is an acceptable and equivalent region for source and destination. The test .asm files are regenerated by round-tripping them through the assembler/disassembler. Note that the <0> region in the tests was a harmless mistake: the compiler translated it to a <0,1,0> source region and a <1> destination region, since <0> isn't valid. Reviewed-by: Sagar Ghuge Part-of: --- diff --git a/src/intel/compiler/brw_eu.cpp b/src/intel/compiler/brw_eu.cpp index 51ae8cdc221..0027b0a3965 100644 --- a/src/intel/compiler/brw_eu.cpp +++ b/src/intel/compiler/brw_eu.cpp @@ -650,7 +650,7 @@ static const struct opcode_desc opcode_descs[] = { { BRW_OPCODE_FORK, 46, "fork", 0, 0, GEN6 }, { BRW_OPCODE_GOTO, 46, "goto", 0, 0, GEN_GE(GEN8) }, { BRW_OPCODE_POP, 47, "pop", 2, 0, GEN_LE(GEN5) }, - { BRW_OPCODE_WAIT, 48, "wait", 1, 0, GEN_LT(GEN12) }, + { BRW_OPCODE_WAIT, 48, "wait", 0, 1, GEN_LT(GEN12) }, { BRW_OPCODE_SEND, 49, "send", 1, 1, GEN_LT(GEN12) }, { BRW_OPCODE_SENDC, 50, "sendc", 1, 1, GEN_LT(GEN12) }, { BRW_OPCODE_SEND, 49, "send", 2, 1, GEN_GE(GEN12) }, diff --git a/src/intel/tools/tests/gen7.5/wait.asm b/src/intel/tools/tests/gen7.5/wait.asm index f94845cd8a1..7f81fcd2253 100644 --- a/src/intel/tools/tests/gen7.5/wait.asm +++ b/src/intel/tools/tests/gen7.5/wait.asm @@ -1,3 +1,3 @@ -wait(1) n0<0>.xUD { align16 WE_all 1N }; -wait(1) n0<0>.yUD { align16 WE_all 1N }; -wait(1) n0<0>.zUD { align16 WE_all 1N }; +wait(1) n0<1>.xUD { align16 WE_all 1N }; +wait(1) n0<1>.yUD { align16 WE_all 1N }; +wait(1) n0<1>.zUD { align16 WE_all 1N }; diff --git a/src/intel/tools/tests/gen7/wait.asm b/src/intel/tools/tests/gen7/wait.asm index f94845cd8a1..7f81fcd2253 100644 --- a/src/intel/tools/tests/gen7/wait.asm +++ b/src/intel/tools/tests/gen7/wait.asm @@ -1,3 +1,3 @@ -wait(1) n0<0>.xUD { align16 WE_all 1N }; -wait(1) n0<0>.yUD { align16 WE_all 1N }; -wait(1) n0<0>.zUD { align16 WE_all 1N }; +wait(1) n0<1>.xUD { align16 WE_all 1N }; +wait(1) n0<1>.yUD { align16 WE_all 1N }; +wait(1) n0<1>.zUD { align16 WE_all 1N }; diff --git a/src/intel/tools/tests/gen8/wait.asm b/src/intel/tools/tests/gen8/wait.asm index 14c0b678e64..864acd0a8e0 100644 --- a/src/intel/tools/tests/gen8/wait.asm +++ b/src/intel/tools/tests/gen8/wait.asm @@ -1,3 +1,3 @@ -wait(1) n0.0<0>UD { align1 WE_all 1N }; -wait(1) n0.1<0>UD { align1 WE_all 1N }; -wait(1) n0.2<0>UD { align1 WE_all 1N }; +wait(1) n0<1>UD { align1 WE_all 1N }; +wait(1) n0.1<1>UD { align1 WE_all 1N }; +wait(1) n0.2<1>UD { align1 WE_all 1N }; diff --git a/src/intel/tools/tests/gen9/wait.asm b/src/intel/tools/tests/gen9/wait.asm index 14c0b678e64..864acd0a8e0 100644 --- a/src/intel/tools/tests/gen9/wait.asm +++ b/src/intel/tools/tests/gen9/wait.asm @@ -1,3 +1,3 @@ -wait(1) n0.0<0>UD { align1 WE_all 1N }; -wait(1) n0.1<0>UD { align1 WE_all 1N }; -wait(1) n0.2<0>UD { align1 WE_all 1N }; +wait(1) n0<1>UD { align1 WE_all 1N }; +wait(1) n0.1<1>UD { align1 WE_all 1N }; +wait(1) n0.2<1>UD { align1 WE_all 1N };