From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 24 Mar 2021 16:10:00 +0000 (+0000)
Subject: make svp64 isa caller unit tests more obvious
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e4de052118ec339f72ef731b1737fcfb27d510b9;p=soc.git

make svp64 isa caller unit tests more obvious
---

diff --git a/src/soc/decoder/isa/test_caller_svp64.py b/src/soc/decoder/isa/test_caller_svp64.py
index 7875dc08..7cc04f40 100644
--- a/src/soc/decoder/isa/test_caller_svp64.py
+++ b/src/soc/decoder/isa/test_caller_svp64.py
@@ -53,19 +53,19 @@ class DecoderTestCase(FHDLTestCase):
 
         # initial values in GPR regfile
         initial_regs = [0] * 32
+        initial_regs[5] = 0x4321
         initial_regs[9] = 0x1234
         initial_regs[10] = 0x1111
-        initial_regs[5] = 0x4321
         initial_regs[6] = 0x2223
         # SVSTATE (in this case, VL=2)
         svstate = SVP64State()
         svstate.vl[0:7] = 2 # VL
         svstate.maxvl[0:7] = 2 # MAXVL
         print ("SVSTATE", bin(svstate.spr.asint()))
-        # copy before running
+        # copy before running, then compute answers
         expected_regs = deepcopy(initial_regs)
-        expected_regs[1] = 0x5555
-        expected_regs[2] = 0x3334
+        expected_regs[1] = initial_regs[5] + initial_regs[9]  # 0x5555
+        expected_regs[2] = initial_regs[6] + initial_regs[10] # 0x3334
 
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, initial_regs, svstate)
@@ -93,7 +93,7 @@ class DecoderTestCase(FHDLTestCase):
         print ("SVSTATE", bin(svstate.spr.asint()))
         # copy before running
         expected_regs = deepcopy(initial_regs)
-        expected_regs[1] = 0x5555
+        expected_regs[1] = initial_regs[5] + initial_regs[9] # 0x5555
 
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, initial_regs, svstate)
@@ -121,8 +121,8 @@ class DecoderTestCase(FHDLTestCase):
         print ("SVSTATE", bin(svstate.spr.asint()))
         # copy before running
         expected_regs = deepcopy(initial_regs)
-        expected_regs[1] = 0x5555
-        expected_regs[2] = 0x5432
+        expected_regs[1] = initial_regs[5] + initial_regs[9]   # 0x5555
+        expected_regs[2] = initial_regs[5] + initial_regs[10]  # 0x5432
 
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, initial_regs, svstate)
@@ -176,8 +176,8 @@ class DecoderTestCase(FHDLTestCase):
         print ("SVSTATE", bin(svstate.spr.asint()))
         # copy before running
         expected_regs = deepcopy(initial_regs)
-        expected_regs[1] = 0
-        expected_regs[2] = 0x3334
+        expected_regs[1] = initial_regs[5] + initial_regs[9]  # 0x0
+        expected_regs[2] = initial_regs[6] + initial_regs[10] # 0x3334
 
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, initial_regs, svstate)