From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 31 May 2020 11:27:45 +0000 (+0100)
Subject: add write_cr to ALU record subset
X-Git-Tag: div_pipeline~725
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e4f0294d825076abfca37096ed7bc3d2457437a8;p=soc.git

add write_cr to ALU record subset
---

diff --git a/src/soc/fu/alu/alu_input_record.py b/src/soc/fu/alu/alu_input_record.py
index a1f6b0a9..f95c16d3 100644
--- a/src/soc/fu/alu/alu_input_record.py
+++ b/src/soc/fu/alu/alu_input_record.py
@@ -17,11 +17,12 @@ class CompALUOpSubset(Record):
                     #'cr = Signal(32, reset_less=True) # NO: this is from the CR SPR
                     #'xerc = XerBits() # NO: this is from the XER SPR
                   ('lk', 1),
-                  ('rc', Layout((("rc", 1), ("rc_ok", 1)))),
-                  ('oe', Layout((("oe", 1), ("oe_ok", 1)))),
+                  ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # Data
+                  ('oe', Layout((("oe", 1), ("oe_ok", 1)))), # Data
                   ('invert_a', 1),
                   ('zero_a', 1),
                   ('invert_out', 1),
+                  ('write_cr', Layout((("data", 3), ("ok", 1)))), # Data
                   ('input_carry', CryIn),
                   ('output_carry', 1),
                   ('input_cr', 1),