From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 29 Aug 2019 00:21:12 +0000 (-0700)
Subject: Specify ice40 family to cells_sim.v using define
X-Git-Tag: working-ls180~1075^2^2~28
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e4f89e01b5710eb9e2e6675a1df13a5a2637b206;p=yosys.git

Specify ice40 family to cells_sim.v using define
---

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index c6de81bd9..2f77c03db 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -238,7 +238,14 @@ struct SynthIce40Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -icells -lib +/ice40/cells_sim.v");
+			std::string define;
+			if (device_opt == "lp")
+				define = "-D ICE40_LX";
+			else if (device_opt == "u")
+				define = "-D ICE40_U";
+			else
+				define = "-D ICE40_HX";
+			run("read_verilog -icells " + define + " -lib +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}